PMM Registers
88
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Power Management Module (PMM) and Supply Voltage Supervisor (SVS)
2.3
PMM Registers
The PMM registers are listed in
. The base address of the PMM module can be found in the
device-specific data sheet. The address offset of each PMM register is given in
The password defined in the PMMCTL0 register controls access to all PMM registers except PM5CTL0.
PM5CTL0 can be accessed without a password. After the correct password is written, the write access is
enabled (this includes byte access to the PMMCTL0 lower byte). The write access is disabled by writing a
wrong password in byte mode to the PMMCTL0 upper byte. Word accesses to PMMCTL0 with a wrong
password triggers a PUC. A write access to a register other than PMMCTL0 while write access is not
enabled causes a PUC.
NOTE:
All registers have word or byte register access. For a generic register
ANYREG
, the suffix
"_L" (
ANYREG_L
) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(
ANYREG_H
) refers to the upper byte of the register (bits 8 through 15).
(1)
PMMCTL1 can be written as word only.
Table 2-1. PMM Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
PMMCTL0
PMM control register 0
Read/write
Word
9640h
00h
PMMCTL0_L
Read/write
Byte
40h
01h
PMMCTL0_H
Read/write
Byte
96h
02h
PMMCTL1
PMM control register 1
Read/write
(1)
Word
9600h
02h
PMMCTL1_L
Read
(1)
Byte
00h
03h
PMMCTL1_H
Read
(1)
Byte
96h
0Ah
PMMIFG
PMM interrupt flag register
Read/write
Word
0000h
0Ah
PMMIFG_L
Read/write
Byte
00h
0Bh
PMMIFG_H
Read/write
Byte
00h
10h
PM5CTL0
Power mode 5 control register 0
Read/write
Word
0001h
10h
PM5CTL0_L
Read/write
Byte
01h
11h
PM5CTL0_H
Read/write
Byte
00h