Timer_B Registers
681
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Timer_B
26.3.1 TBxCTL Register
Timer_B x Control Register
Figure 26-16. TBxCTL Register
15
14
13
12
11
10
9
8
Reserved
TBCLGRPx
CNTL
Reserved
TBSSEL
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
7
6
5
4
3
2
1
0
ID
MC
Reserved
TBCLR
TBIE
TBIFG
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
w-(0)
rw-(0)
rw-(0)
Table 26-6. TBxCTL Register Description
Bit
Field
Type
Reset
Description
15
Reserved
R
0h
Reserved. Always reads as 0.
14-13
TBCLGRP
RW
0h
TBxCLn group
00b = Each TBxCLn latch loads independently.
01b = TBxCL2 (TBxCCR1 CLLD bits control the update);
TBxCL4 (TBxCCR3 CLLD bits control the update); TBxCL6
(TBxCCR5 CLLD bits control the update); TBxCL0 independent
10b = TBxCL3 (TBxCCR1 CLLD bits control the update);
TBxCL6 (TBxCCR4 CLLD bits control the update); TBxCL0
independent
11b = TBxCL6
(TBxCCR1 CLLD bits control the update)
12-11
CNTL
RW
0h
Counter length
00b = 16-bit, TBxR(max) = 0FFFFh
01b = 12-bit, TBxR(max) = 0FFFh
10b = 10-bit, TBxR(max) = 03FFh
11b = 8-bit, TBxR(max) = 0FFh
10
Reserved
R
0h
Reserved. Always reads as 0.
9-8
TBSSEL
RW
0h
Timer_B clock source select
00b = TBxCLK
01b = ACLK
10b = SMCLK
11b = INCLK
7-6
ID
RW
0h
Input divider. These bits, along with the TBIDEX bits, select the divider for the
input clock.
00b = /1
01b = /2
10b = /4
11b = /8
5-4
MC
RW
0h
Mode control. Setting MC = 00h when Timer_B is not in use conserves power.
00b = Stop mode: Timer is halted
01b = Up mode: Timer counts up to TBxCL0
10b = Continuous mode: Timer counts up to the value set by CNTL
11b = Up/down mode: Timer counts up to TBxCL0 and down to 0000h
3
Reserved
R
0h
Reserved. Always reads as 0.
2
TBCLR
RW
0h
Timer_B clear. Setting this bit clears TBR, the clock divider logic (the divider
setting remains unchanged), and the count direction. The TBCLR bit is
automatically reset and is always read as zero.
1
TBIE
RW
0h
Timer_B interrupt enable. This bit enables the TBIFG interrupt request.
0b = Interrupt disabled
1b = Interrupt enabled