Clock System Operation
100
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Clock System (CS) Module
The function of the ACLKREQEN, MCLKREQEN, and SMCLKREQEN bits are dependent upon which
power mode is selected; that is, they do not have an effect across all power modes. For example,
ACLKREQEN is used to enable or disable ACLK requests. It is effective only in LPM4, because ACLK is
always active in all other modes (AM, LPM0, LPM1, LPM2, LPM3). SMCLKREQEN is used to enable or
disable SMCLK requests. When SMCLKOFF = 0 and in AM, LPM0, or LPM1, it is a don't care, because
SMCLK is always on in these cases. For SMCLKOFF = 0 and in LPM2, LPM3, and LPM4,
SMCLKREQEN can be used to enable or disable SMCLK requests, because SMCLK is normally off in
these modes. When SMCLKOFF = 1, SMCLKREQEN can be used to enable or disable SMCLK requests,
because SMCLK is normally off in all power modes under this condition. This is summarized in
(1)
LFXTCLK is available directly as the clock source to the RTC module.
Table 3-2. System Clocks, Power Modes, and Clock Requests
Mode
System Clocks
MCLK
ACLK
SMCLK
SMCLKOFF = 0
SMCLKOFF = 1
MCLKREQEN
= 0 and Clock
Requested
MCLKREQEN
= 1 and Clock
Requested
ACLKREQEN
= 0 and Clock
Requested
ACLKREQEN
= 1 and Clock
Requested
SMCLKREQEN
= 0 and Clock
Requested
SMCLKREQEN
= 1 and Clock
Requested
SMCLKREQEN
= 0 and Clock
Requested
SMCLKREQEN
= 1 and Clock
Requested
AM
Active
Active
Active
Active
Active
Active
Disabled
Active
LPM0
Disabled
Active
Active
Active
Active
Active
Disabled
Active
LPM1
Disabled
Active
Active
Active
Active
Active
Disabled
Active
LPM2
Disabled
Active
Active
Active
Disabled
Active
Disabled
Active
LPM3
Disabled
Active
Active
Active
Disabled
Active
Disabled
Active
LPM4
Disabled
Active
Disabled
Active
Disabled
Active
Disabled
Active
LPM3.5
Disabled
Disabled
Disabled
(1)
Disabled
Disabled
Disabled
Disabled
Disabled
LPM4.5
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
3.2.8 CS Module Fail-Safe Operation
The CS module incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for
LFXT and HFXT as shown in
. The available fault conditions are:
•
Low-frequency oscillator fault (LFXTOFFG) for LFXT
•
High-frequency oscillator fault (HFXTOFFG) for HFXT
•
External clock signal faults for all bypass modes; that is, LFXTBYPASS = 1 or HFXTBYPASS = 1
The crystal oscillator fault bits LFXTOFFG and HFXTOFFG are set if the corresponding crystal oscillator is
turned on and not operating properly. Once set, the fault bits remain set until reset in software, even if the
fault condition no longer exists. If the user clears the fault bits and the fault condition still exists, the fault
bits are automatically set; otherwise, they remain cleared.
The OFIFG oscillator-fault interrupt flag is set and latched at POR or when any oscillator fault (LFXTOFFG
or HFXTOFFG) is detected. When OFIFG is set and OFIE is set, the OFIFG requests a user NMI. When
the interrupt is granted, the OFIE is not reset automatically as it is in previous MSP430 families. It is no
longer required to reset the OFIE. NMI entry and exit circuitry removes this requirement. The OFIFG flag
must be cleared by software. The source of the fault can be identified by checking the individual fault bits.
If LFXT is sourcing any system clock (ACLK, MCLK, or SMCLK) and a fault is detected, the system clock
is automatically switched to LFMODCLK for its clock source. The LFXT fault logic works in all power
modes, including LPM3.5. Similarly, if HFXT is sourcing MCLK or SMCLK, and a fault is detected, the
system clock is automatically switched to MODCLK for its clock source. By default, the HFXT fault logic
works in all power modes except LPM3.5 or LPM4.5, because high-frequency operation in these modes is
not supported. The fail-safe logic does not change the respective SELA, SELM, and SELS bit settings.
The fail-safe mechanism behaves the same in normal and bypass modes. Reconfigure the CS settings
and follow the instructions in
after wakeup from LPM3.5 or LPM4.5, because all CS registers
are reset to default values.