Texas Instruments MSP430FR57 Series, User Manual, Page: 524 / 578

eUSCI_B SPI Registers
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19.5 eUSCI_B SPI Registers
The eUSCI_B registers applicable in SPI mode and their address offsets are listed in Table 19-11 . The
base addresses can be found in the device-specific data sheet.
Table 19-11. eUSCI_B SPI Registers
Offset Acronym Register Name Type Access Reset Section
00h UCBxCTLW0 eUSCI_Bx Control Word 0 Read/write Word 01C1h Section 19.5.1
00h UCBxCTL1 eUSCI_Bx Control 1 Read/write Byte C1h
01h UCBxCTL0 eUSCI_Bx Control 0 Read/write Byte 01h
06h UCBxBRW eUSCI_Bx Bit Rate Control Word Read/write Word 0000h Section 19.5.2
06h UCBxBR0 eUSCI_Bx Bit Rate Control 0 Read/write Byte 00h
07h UCBxBR1 eUSCI_Bx Bit Rate Control 1 Read/write Byte 00h
08h UCBxSTATW eUSCI_Bx Status Read/write Word 00h Section 19.5.3
0Ch UCBxRXBUF eUSCI_Bx Receive Buffer Read/write Word 00h Section 19.5.4
0Eh UCBxTXBUF eUSCI_Bx Transmit Buffer Read/write Word 00h Section 19.5.5
2Ah UCBxIE eUSCI_Bx Interrupt Enable Read/write Word 00h Section 19.5.6
2Ch UCBxIFG eUSCI_Bx Interrupt Flag Read/write Word 02h Section 19.5.7
2Eh UCBxIV eUSCI_Bx Interrupt Vector Read Word 0000h Section 19.5.8
524 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU272C – May 2011 – Revised November 2013
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