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DMA Operation

7.2.4 Halting Executing Instructions for DMA Transfers

The DMARMWDIS bit controls when the CPU is halted for DMA transfers. When DMARMWDIS = 0, the
CPU is halted immediately and the transfer begins when a trigger is received. In this case, it is possible
that CPU read-modify-write operations can be interrupted by a DMA transfer. When DMARMWDIS = 1,
the CPU finishes the currently executing read-modify-write operation before the DMA controller halts the
CPU and the transfer begins (see

Table 7-2

).

Table 7-2. DMA Trigger Operation

Module

Operation

DMA

A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer
starts.
A transfer is triggered when the DMAxIFG flag is set. DMA0IFG triggers channel 1, DMA1IFG triggers channel 2,
and DMA2IFG triggers channel 0. None of the DMAxIFG flags are automatically reset when the transfer starts.
A transfer is triggered by the external trigger DMAE0.

Timer_A

A transfer is triggered when the TAxCCR0 CCIFG flag is set. The TAxCCR0 CCIFG flag is automatically reset
when the transfer starts. If the TAxCCR0 CCIE bit is set, the TAxCCR0 CCIFG flag does not trigger a transfer.
A transfer is triggered when the TAxCCR2 CCIFG flag is set. The TAxCCR2 CCIFG flag is automatically reset
when the transfer starts. If the TAxCCR2 CCIE bit is set, the TAxCCR2 CCIFG flag does not trigger a transfer.

Timer_B

A transfer is triggered when the TBxCCR0 CCIFG flag is set. The TBxCCR0 CCIFG flag is automatically reset
when the transfer starts. If the TBxCCR0 CCIE bit is set, the TBxCCR0 CCIFG flag does not trigger a transfer.
A transfer is triggered when the TBxCCR2 CCIFG flag is set. The TBxCCR2 CCIFG flag is automatically reset
when the transfer starts. If the TBxCCR2 CCIE bit is set, the TBxCCR2 CCIFG flag does not trigger a transfer.

eUSCI_Ax

A transfer is triggered when eUSCI_Ax receives new data. UCAxRXIFG is automatically reset when the transfer
starts. If UCAxRXIE is set, the UCAxRXIFG does not trigger a transfer.
A transfer is triggered when eUSCI_Ax is ready to transmit new data. UCAxTXIFG is automatically reset when
the transfer starts. If UCAxTXIE is set, the UCAxTXIFG does not trigger a transfer.

eUSCI_Bx

A transfer is triggered when eUSCI_Bx receives new data. UCBxRXIFG is automatically reset when the transfer
starts. If UCBxRXIE is set, the UCBxRXIFG does not trigger a transfer.
A transfer is triggered when eUSCI_Bx is ready to transmit new data. UCBxTXIFG is automatically reset when
the transfer starts. If UCBxTXIE is set, the UCBxTXIFG does not trigger a transfer.

ADC10_B

A transfer is triggered by an ADC10IFG0 flag. A transfer is triggered when the conversion is completed and the
ADC10IFG0 is set. Setting the ADC10IFG0 with software does not trigger a transfer. The ADC10IFG0 flag is
automatically reset when the ADC10MEM0 register is accessed by the DMA controller.

MPY

A transfer is triggered when the hardware multiplier is ready for a new operand.

Reserved

No transfer is triggered.

7.2.5 Stopping DMA Transfers

There are two ways to stop DMA transfers in progress:

•

A single, block, or burst-block transfer may be stopped with an NMI, if the ENNMI bit is set in register
DMACTL1.

•

A burst-block transfer may be stopped by clearing the DMAEN bit.

7.2.6 DMA Channel Priorities

The default DMA channel priorities are DMA0 through DMA7. If two or three triggers happen
simultaneously or are pending, the channel with the highest priority completes its transfer (single, block, or
burst-block transfer) first, then the second priority channel, then the third priority channel. Transfers in
progress are not halted if a higher-priority channel is triggered. The higher-priority channel waits until the
transfer in progress completes before starting.

The DMA channel priorities are configurable with the ROUNDROBIN bit. When the ROUNDROBIN bit is
set, the channel that completes a transfer becomes the lowest priority. The order of the priority of the
channels always stays the same, DMA0-DMA1-DMA2, for example, for three channels. When the
ROUNDROBIN bit is cleared, the channel priority returns to the default priority.

275

SLAU272C – May 2011 – Revised November 2013

DMA Controller

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Copyright © 2011–2013, Texas Instruments Incorporated

Summary of Contents for MSP430FR57 Series

Page 1: ...MSP430FR57xx Family User s Guide Literature Number SLAU272C May 2011 Revised November 2013 ...

Page 2: ...in RST NMI Configuration 40 1 8 Configuring JTAG Pins 40 1 9 Vacant Memory Space 41 1 10 Boot Code 41 1 11 Bootstrap Loader BSL 41 1 12 JTAG Mailbox JMB System 41 1 12 1 JMB Configuration 42 1 12 2 JMBOUT0 and JMBOUT1 Outgoing Mailbox 42 1 12 3 JMBIN0 and JMBIN1 Incoming Mailbox 42 1 12 4 JMB NMI Usage 42 1 13 JTAG and SBW Lock Mechanism Using the Electronic Fuse 42 1 13 1 JTAG and SBW Lock Withou...

Page 3: ...ency Oscillator VLO 73 3 2 3 XT1 Oscillator 73 3 2 4 XT2 Oscillator 74 3 2 5 Digitally Controlled Oscillator DCO 74 3 2 6 Operation From Low Power Modes Requested by Peripheral Modules 75 3 2 7 CS Module Fail Safe Operation 76 3 2 8 Synchronization of Clock Signals 78 3 3 Module Oscillator MODOSC 78 3 3 1 MODOSC Operation 78 3 4 CS Registers 79 3 4 1 CSCTL0 Register 80 3 4 2 CSCTL1 Register 81 3 4...

Page 4: ...al Wait State Control 245 5 5 2 Automatic Wait State Control 246 5 5 3 Wait State and Cache Hit 246 5 5 4 Safe Access 246 5 6 FRAM ECC 246 5 7 FRCTL Registers 247 5 7 1 FRCTL0 Register 248 5 7 2 GCCTL0 Register 249 5 7 3 GCCTL1 Register 250 6 Memory Protection Unit MPU 251 6 1 Memory Protection Unit MPU Introduction 252 6 2 MPU Segments 253 6 2 1 Main Memory Segments 253 6 2 2 Segment Border Setti...

Page 5: ...xOUT 294 8 2 3 Direction Registers PxDIR 294 8 2 4 Pullup or Pulldown Resistor Enable Registers PxREN 294 8 2 5 Function Select Registers PxSEL0 PxSEL1 295 8 2 6 Port Interrupts 295 8 3 I O Configuration 297 8 3 1 Configuration After Reset 297 8 3 2 Configuration of Unused Port Pins 297 8 3 3 Configuration for LPMx 5 Low Power Modes 298 8 4 Digital I O Registers 300 8 4 1 P1IV Register 313 8 4 2 P...

Page 6: ...t 343 11 2 6 Timer_A Interrupts 347 11 3 Timer_A Registers 349 11 3 1 TAxCTL Register 350 11 3 2 TAxR Register 351 11 3 3 TAxCCTLn Register 352 11 3 4 TAxCCRn Register 354 11 3 5 TAxIV Register 354 11 3 6 TAxEX0 Register 355 12 Timer_B 356 12 1 Timer_B Introduction 357 12 1 1 Similarities and Differences From Timer_A 357 12 2 Timer_B Operation 359 12 2 1 16 Bit Timer Counter 359 12 2 2 Starting th...

Page 7: ...r Hexadecimal Format 399 13 3 17 RTCYEAR Register BCD Format 399 13 3 18 RTCAMIN Register Hexadecimal Format 400 13 3 19 RTCAMIN Register BCD Format 400 13 3 20 RTCAHOUR Register Hexadecimal Format 401 13 3 21 RTCAHOUR Register BCD Format 401 13 3 22 RTCADOW Register 402 13 3 23 RTCADAY Register Hexadecimal Format 403 13 3 24 RTCADAY Register BCD Format 403 13 3 25 RTCPS0CTL Register 404 13 3 26 R...

Page 8: ...er 455 16 3 5 ADC10MEM0 Register 2s Complement Format 455 16 3 6 ADC10MCTL0 Register 456 16 3 7 ADC10HI Register 457 16 3 8 ADC10HI Register 2s Complement Format 457 16 3 9 ADC10LO Register 458 16 3 10 ADC10LO Register 2s Complement Format 458 16 3 11 ADC10IE Register 459 16 3 12 ADC10IFG Register 460 16 3 13 ADC10IV Register 461 17 Comparator_D 462 17 1 Comparator_D Introduction 463 17 2 Comparat...

Page 9: ...xCTLW1 Register 496 18 4 3 UCAxBRW Register 497 18 4 4 UCAxMCTLW Register 497 18 4 5 UCAxSTATW Register 498 18 4 6 UCAxRXBUF Register 499 18 4 7 UCAxTXBUF Register 499 18 4 8 UCAxABCTL Register 500 18 4 9 UCAxIRCTL Register 501 18 4 10 UCAxIE Register 502 18 4 11 UCAxIFG Register 503 18 4 12 UCAxIV Register 504 19 Enhanced Universal Serial Communication Interface eUSCI SPI Mode 505 19 1 Enhanced U...

Page 10: ..._B Module in I2 C Mode With Low Power Modes 549 20 3 11 eUSCI_B Interrupts in I2 C Mode 550 20 4 eUSCI_B I2C Registers 553 20 4 1 UCBxCTLW0 Register 554 20 4 2 UCBxCTLW1 Register 556 20 4 3 UCBxBRW Register 558 20 4 4 UCBxSTATW 558 20 4 5 UCBxTBCNT Register 559 20 4 6 UCBxRXBUF Register 560 20 4 7 UCBxTXBUF 560 20 4 8 UCBxI2COA0 Register 561 20 4 9 UCBxI2COA1 Register 562 20 4 10 UCBxI2COA2 Regist...

Page 11: ... PMMIFG Register 68 2 6 PM5CTL0 Register 69 3 1 Clock System Block Diagram 72 3 2 Module Request Clock System 75 3 3 Oscillator Fault Logic 77 3 4 Switch MCLK from DCOCLK to XT1CLK 78 3 5 CSCTL0 Register 80 3 6 CSCTL1 Register 81 3 7 CSCTL2 Register 82 3 8 CSCTL3 Register 83 3 9 CSCTL4 Register 84 3 10 CSCTL5 Register 85 3 11 CSCTL6 Register 86 4 1 MSP430X CPU Block Diagram 89 4 2 PC Storage on th...

Page 12: ...RET Instruction 169 4 38 Destination Operand Arithmetic Shift Left 171 4 39 Destination Operand Carry Left Shift 172 4 40 Rotate Right Arithmetically RRA B and RRA W 173 4 41 Rotate Right Through Carry RRC B and RRC W 174 4 42 Swap Bytes in Memory 181 4 43 Swap Bytes in a Register 181 4 44 Rotate Left Arithmetically RLAM W and RLAM A 208 4 45 Destination Operand Arithmetic Shift Left 209 4 46 Dest...

Page 13: ...7 14 DMAxSZ Register 290 7 15 DMAIV Register 291 8 1 P1IV Register 313 8 2 P2IV Register 313 8 3 P3IV Register 314 8 4 P4IV Register 314 8 5 PxIN Register 315 8 6 PxOUT Register 315 8 7 PxDIR Register 315 8 8 PxREN Register 316 8 9 PxSEL0 Register 316 8 10 PxSEL1 Register 316 8 11 PxSELC Register 317 8 12 PxIES Register 317 8 13 PxIE Register 317 8 14 PxIFG Register 318 9 1 LFSR Implementation of ...

Page 14: ...Continuous Mode Flag Setting 361 12 6 Continuous Mode Time Intervals 361 12 7 Up Down Mode 362 12 8 Up Down Mode Flag Setting 362 12 9 Output Unit in Up Down Mode 363 12 10 Capture Signal SCS 1 364 12 11 Capture Cycle 364 12 12 Output Example Timer in Up Mode 367 12 13 Output Example Timer in Continuous Mode 368 12 14 Output Example Timer in Up Down Mode 369 12 15 Capture Compare TBxCCR0 Interrupt...

Page 15: ...ion 416 14 4 Saturation Flow Chart 418 14 5 Multiplication Flow Chart 420 14 6 MPY32CTL0 Register 426 15 1 REF Block Diagram 428 15 2 REFCTL0 Register 432 16 1 ADC10_B Block Diagram 435 16 2 Analog Multiplexer 436 16 3 Extended Sample Mode 438 16 4 Pulse Sample Mode 438 16 5 Analog Input Equivalent Circuit 439 16 6 Single Channel Single Conversion Mode 440 16 7 Sequence of Channels Mode 441 16 8 R...

Page 16: ...to Baud Rate Detection Break Synch Sequence 482 18 6 Auto Baud Rate Detection Synch Field 482 18 7 UART vs IrDA Data Format 483 18 8 Glitch Suppression eUSCI_A Receive Not Started 485 18 9 Glitch Suppression eUSCI_A Activated 485 18 10 BITCLK Baud Rate Timing With UCOS16 0 486 18 11 Receive Error 490 18 12 UCAxCTLW0 Register 495 18 13 UCAxCTLW1 Register 496 18 14 UCAxBRW Register 497 18 15 UCAxMCT...

Page 17: ...e 540 20 11 I2 C Slave 10 Bit Addressing Mode 541 20 12 I2 C Master Transmitter Mode 543 20 13 I2 C Master Receiver Mode 545 20 14 I2 C Master 10 Bit Addressing Mode 546 20 15 Arbitration Procedure Between Two Master Transmitters 546 20 16 Synchronization of Two I2 C Clock Generators During Arbitration 547 20 17 UCBxCTLW0 Register 554 20 18 UCBxCTLW1 Register 556 20 19 UCBxBRW Register 558 20 20 U...

Page 18: ...PMM Registers 66 2 2 PMMCTL0 Register Description 67 2 3 PMMIFG Register Description 68 2 4 PM5CTL0 Register Description 69 3 1 System Clocks vs Power Modes and Clock Requests 76 3 2 CS Registers 79 3 3 CSCTL0 Register Description 80 3 4 CSCTL1 Register Description 81 3 5 CSCTL2 Register Description 82 3 6 CSCTL3 Register Description 83 3 7 CSCTL4 Register Description 84 3 8 CSCTL5 Register Descri...

Page 19: ...on 260 6 7 MPUSAM Register Description 261 6 8 MPUIV Register Description 263 7 1 DMA Transfer Modes 268 7 2 DMA Trigger Operation 275 7 3 Maximum Single Transfer DMA Cycle Time 276 7 4 DMA Registers 279 7 5 DMACTL0 Register Description 281 7 6 DMACTL1 Register Description 282 7 7 DMACTL2 Register Description 283 7 8 DMACTL3 Register Description 284 7 9 DMACTL4 Register Description 285 7 10 DMAxCT...

Page 20: ...66 12 5 Timer_B Registers 372 12 6 TBxCTL Register Description 373 12 7 TBxR Register Description 375 12 8 TBxCCTLn Register Description 376 12 9 TBxCCRn Register Description 378 12 10 TBxIV Register Description 379 12 11 TBxEX0 Register Description 380 13 1 RTC_B Registers 389 13 2 RTCCTL0 Register Description 391 13 3 RTCCTL1 Register Description 392 13 4 RTCCTL2 Register Description 393 13 5 RT...

Page 21: ...32CTL0 Register Description 426 15 1 REF Control of Reference System REFMSTR 1 Default 429 15 2 REF Registers 431 15 3 REFCTL0 Register Description 432 16 1 Conversion Mode Summary 439 16 2 ADC10_B Registers 449 16 3 ADC10CTL0 Register Description 450 16 4 ADC10CTL1 Register Description 452 16 5 ADC10CTL2 Register Description 454 16 6 ADC10MEM0 Register Description 455 16 7 ADC10MEM0 Register Desc...

Page 22: ...CAxSTATW Register Description 518 19 6 UCAxRXBUF Register Description 519 19 7 UCAxTXBUF Register Description 520 19 8 UCAxIE Register Description 521 19 9 UCAxIFG Register Description 522 19 10 UCAxIV Register Description 523 19 11 eUSCI_B SPI Registers 524 19 12 UCBxCTLW0 Register Description 525 19 13 UCBxBRW Register Description 527 19 14 UCBxSTATW Register Description 527 19 15 UCBxRXBUF Regi...

Page 23: ...on 563 20 16 UCBxADDMASK Register Description 564 20 17 UCBxI2CSA Register Description 564 20 18 UCBxIE Register Description 565 20 19 UCBxIFG Register Description 567 20 20 UCBxIV Register Description 569 21 1 EEM Configurations 574 23 SLAU272C May 2011 Revised November 2013 List of Tables Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 24: ... for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct t...

Page 25: ...ister Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit and the initial condition Register Bit Accessibility and Initial Condition Key Bit Accessibility rw Read write r Read only r0 Read as 0 r1 Read as 1 w Write only w0 Write as 0 w1 Write as 1 w No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 ...

Page 26: ...et and NMIs Topic Page 1 1 System Control Module SYS Introduction 27 1 2 System Reset and Initialization 27 1 3 Interrupts 29 1 4 Operating Modes 35 1 5 Principles for Low Power Applications 39 1 6 Connection of Unused Pins 40 1 7 Reset Pin RST NMI Configuration 40 1 8 Configuring JTAG Pins 40 1 9 Vacant Memory Space 41 1 10 Boot Code 41 1 11 Bootstrap Loader BSL 41 1 12 JTAG Mailbox JMB System 41...

Page 27: ... PMM and SVS chapter for details A POR is always generated when a BOR is generated but a BOR is not generated by a POR The following events trigger a POR BOR signal Software POR event see the PMM and SVS chapter for details A PUC is always generated when a POR is generated but a POR is not generated by a PUC The following events trigger a PUC POR signal Watchdog timer expiration when watchdog mode...

Page 28: ... WDTIFG Watchdog Timer s EN from port wakeup logic s PUC Logic Module PUCs MCLK notRST Delay clr clr clr System Reset and Initialization www ti com Figure 1 1 BOR POR and PUC Reset Circuit 28 System Resets Interrupts and Operating Modes System Control Module SLAU272C May 2011 Revised November 2013 SYS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 29: ...ser software must initialize the device for the application requirements The following must occur Initialize the stack pointer SP typically to the top of RAM when available otherwise FRAM location Initialize the watchdog to the requirements of the application Configure peripheral modules to the requirements of the application NOTE A device that is unprogrammed or blank is defined as having its res...

Page 30: ...t can be generated by following sources FRAM errors see the FRAM Controller chapter for details Vacant memory access JTAG mailbox JMB event NOTE The number and types of NMI sources may vary from device to device See the device specific data sheet for all NMI sources available 1 3 2 SNMI Timing Consecutive SNMIs that occur at a higher rate than they can be handled interrupt storm allow the main pro...

Page 31: ...remain set for servicing by software 6 All bits of SR are cleared except SCG0 thereby terminating any low power mode Because the GIE bit is cleared further interrupts are disabled 7 The content of the interrupt vector is loaded into the PC the program continues with the interrupt service routine at that address Figure 1 3 Interrupt Processing NOTE Enable and Disable Interrupt Due to the pipelined ...

Page 32: ...pts the routine regardless of the interrupt priorities 1 3 6 Interrupt Vectors The interrupt vectors are located in the address range 0FFFFh to 0FF80h for a maximum of 64 interrupt sources A vector is programmed by the user and points to the start location of the corresponding interrupt service routine Table 1 1 is an example of the interrupt vectors available See the device specific data sheet fo...

Page 33: ...d BOR POR or PUC reset sources of all the other modules They are combined into three interrupt vectors The interrupt vector registers SYSRSTIV SYSSNIV SYSUNIV are used to determine which flags requested an interrupt or a reset The interrupt with the highest priority of a group when enabled generates a number in the corresponding SYSRSTIV SYSSNIV SYSUNIV register This number can be directly added t...

Page 34: ...tor 10 Reserved for future usage JMP RSVD4_ISR Vector 12 Reserved for future usage JMP ACCV_ISR Vector 14 ACCVIFG JMP VMA_ISR Vector 16 VMAIFG JMP JMBI_ISR Vector 18 JMBINIFG JMP JMBO_ISR Vector 20 JMBOUTIFG JMP SBD_ISR Vector 22 SBDIFG DBD_ISR Vector 2 DBDIFG Task_2 starts here RETI Return ACCTIM_ISR Vector 4 Task_4 starts here RETI Return RSVD1_ISR Vector 6 Task_6 starts here RETI Return RSVD2_I...

Page 35: ...may also be disabled with their individual control register settings All I O port pins RAM and registers are unchanged Wakeup from LPM0 through LPM4 is possible through all enabled interrupts When LPMx 5 LPM3 5 or LPM4 5 is entered the voltage regulator of the Power Management Module PMM is disabled All RAM and register contents are lost Although the I O register contents are lost the I O pin stat...

Page 36: ...optional RTC VCORE CPUOFF 1 OSCOFF 0 SCG0 0 SCG1 0 CPUOFF 1 OSCOFF 0 SCG0 1 SCG1 0 CPUOFF 1 OSCOFF 0 SCG0 0 SCG1 1 CPUOFF 1 OSCOFF 0 SCG0 1 SCG1 1 CPUOFF 1 OSCOFF 1 SCG0 1 SCG1 1 PMMREGOFF 1 PMM WDT CS FRAM Password violation to LPMx 5 From active mode Events Operating modes Reset phases Arbitrary transitions Any enabled interrupt and NMI performs this transition An enabled reset always restarts t...

Page 37: ...tails 1 1 1 1 LPM4 5 When PMMREGOFF 1 regulator is disabled No memory retention In this mode all clock sources are disabled that is no RTC operation is possible 1 This bit is automatically reset when exiting low power modes See Section 1 4 2 for details 2 The low power modes and hence the system clocks can be affected by the clock request system See the Clock System chapter for details 1 4 1 Low P...

Page 38: ...r low power modes LPMx 5 when used properly gives the lowest power consumption available on a device To achieve this entry to LPMx 5 disables the LDO of the PMM module which removes the supply voltage from the core of the device Because the supply voltage is removed from the core all register contents and SRAM contents are lost Exit from LPMx 5 causes a BOR event which forces a complete reset of t...

Page 39: ...s are automatically locked to the current state Upon exit from LPMx 5 the I O pin conditions remain locked until the application unlocks them See the Digital I O chapter for complete details If LPM3 5 was in effect RTC operation continues uninterrupted upon wakeup The program flow for exiting LPMx 5 is 1 Enter system reset service routine a Reconfigure system as required for the application b Reco...

Page 40: ...d as an external NMI source The external NMI is edge sensitive and its edge is selectable by SYSNMIIES Setting the NMIIE enables the interrupt of the external NMI Upon an external NMI event the NMIIFG is set The RST NMI pin can have either a pullup or pulldown present or not SYSRSTUP selects either pullup or pulldown and SYSRSTRE causes the pullup or pulldown to be enabled or not If the RST NMI pi...

Page 41: ...am address or by applying the standard reset sequence Access to the device memory via the BSL is protected against misuse by a user defined password Two BSL signatures BSL Signature 1 memory location 0FF84h and BSL Signature 2 memory location 0FF86h reside in FRAM and can be used to control the behavior of the BSL Writing 05555h to BSL Signature 1 or BSL Signature 2 disables the BSL function and a...

Page 42: ...JMBOUT0 has been read by the JTAG port and is ready to receive data In 32 bit mode JMBOUTIFG is set when both JMBOUT0 and JMBOUT1 has been read by the JTAG port and are ready to receive data If JMBOUTIE is set these events cause a system NMI In 16 bit mode JMBOUTIFG is cleared automatically when data is written to JMBOUT0 In 32 bit mode JMBOUTIFG Is cleared automatically when data is written to bo...

Page 43: ...A55Ah and 01E1Eh in JMBIN0 and JMBIN1 respectively the device is expecting a password to be applied The entered password is compared to the password that is stored in the device password memory locations If they match the device unlocks the JTAG and SBW to the complete JTAG command set until the next BOR event occurs NOTE Memory locations 0FF80h through 0FFFFh may also be used for interrupt vector...

Page 44: ...TLV tag length value TLV structure containing the various descriptors Any other value than 80h read at address location 00FF0h indicates the device is of an older family and contains a flat descriptor beginning at location 0FF0h The information block shown in Figure 1 6 contains the device ID die revisions firmware revisions and other manufacturer and tool related information The length of the des...

Page 45: ...rved for future use Reserved 15h Reserved for future use Reserved 16h 1Bh Reserved for future use BSLTAG 1Ch BSL Configuration Reserved 1Dh FDh Reserved for future use TAGEXT FEh Tag extender Each tag field is unique to its respective descriptor and is always followed by a length field The length field is one byte if the tag value is 01h through 0FDh and represents the length of the descriptor in ...

Page 46: ... voltage available 1 5 V 2 0 V and 2 5 V The reference voltages are measured at room temperature The measured values are normalized by 1 5 V 2 0 V or 2 5 V before being stored into the TLV structure as shown in Equation 2 2 In this way a conversion result is corrected by multiplying it with the CAL_15VREF_FACTOR or CAL_20VREF_FACTOR CAL_25VREF_FACTOR and dividing the result by 215 as shown in Equa...

Page 47: ... as a twos complement number in the TLV structure The offset error correction is done by adding the CAL_ADC_OFFSET to the conversion result 4 The gain of the ADC12 is calculated by Equation 5 5 The conversion result is gain corrected by multiplying it with the CAL_ADC_GAIN_FACTOR and dividing the result by 215 6 If both gain and offset are corrected the gain correction is done first 7 1 14 3 3 Tem...

Page 48: ... the length of the configuration option field BSL_CIF_CONFIG The BSL configuration cannot be changed by the user Table 1 8 BSL Configuration Tags BSL Configuration TAG 1Ch Length Depends on the BSL_COM_IF value actual 02h for UART or I2C Low Byte BSL_COM_IF High Byte BSL_CIF_CONFIG 0 Low Byte BSL_CIF_CONFIG 1 optional High Byte BSL_CIF_CONFIG 2 optional Low Byte BSL_CIF_CONFIG 3 optional High Byte...

Page 49: ... suffix _L ANYREG_L refers to the lower byte of the register bits 0 through 7 The suffix _H ANYREG_H refers to the upper byte of the register bits 8 through 15 Table 1 11 SFR Registers Offset Acronym Register Name Type Access Reset Section 00h SFRIE1 Interrupt Enable Read write Word 0000h Section 1 15 1 00h SFRIE1_L IE1 Read write Byte 00h 01h SFRIE1_H IE2 Read write Byte 00h 02h SFRIFG1 Interrupt...

Page 50: ...ds as 0 4 NMIIE RW 0h NMI pin interrupt enable 0b Interrupts disabled 1b Interrupts enabled 3 VMAIE RW 0h Vacant memory access interrupt enable 0b Interrupts disabled 1b Interrupts enabled 2 Reserved R 0h Reserved Always reads as 0 1 OFIE RW 0h Oscillator fault interrupt enable 0b Interrupts disabled 1b Interrupts enabled 0 WDTIE RW 0h Watchdog timer interrupt enable This bit enables the WDTIFG in...

Page 51: ...w message from the CPU In 32 bit mode JMBMODE 1 JMBO0 and JMBO1 have been received by the JTAG module and are ready for new messages from the CPU 6 JMBINIFG RW 0h JTAG mailbox input interrupt flag 0b No interrupt pending When in 16 bit mode JMBMODE 0 this bit is cleared automatically when JMBI0 is read by the CPU When in 32 bit mode JMBMODE 1 this bit is cleared automatically when both JMBI0 and J...

Page 52: ...interval mode WDTIFG is reset automatically by servicing the interrupt or can be reset by software Because other bits in SFRIFG1 may be used for other modules it is recommended to set or clear WDTIFG by using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0b No interrupt pending 1b Interrupt pending 52 System Resets Interrupts and Operating Modes System Control Module SLAU272C...

Page 53: ...own resistor at the RST NMI pin is enabled 2 SYSRSTUP RW 1h Reset resistor pin pullup or pulldown 0b Pulldown is selected 1b Pullup is selected 1 SYSNMIIES RW 0h NMI edge select This bit selects the interrupt edge for the NMI when SYSNMI 1 Modifying this bit can trigger an NMI Modify this bit when SYSNMI 0 to avoid triggering an accidental NMI 0b NMI on rising edge 1b NMI on falling edge 0 SYSNMI ...

Page 54: ...tion 1 16 2 06h SYSJMBC_L Read write Byte 0Ch 07h SYSJMBC_H Read write Byte 00h 08h SYSJMBI0 JTAG Mailbox Input 0 Read write Word 0000h Section 1 16 3 08h SYSJMBI0_L Read write Byte 00h 09h SYSJMBI0_H Read write Byte 00h 0Ah SYSJMBI1 JTAG Mailbox Input 1 Read write Word 0000h Section 1 16 4 0Ah SYSJMBI1_L Read write Byte 00h 0Bh SYSJMBI1_H Read write Byte 00h 0Ch SYSJMBO0 JTAG Mailbox Output 0 Rea...

Page 55: ... Dedicated JTAG pins explicit 4 wire JTAG mode selection 4 SYSBSLIND R 0h BSL entry indication This bit indicates a BSL entry sequence detected on the Spy Bi Wire pins 0b No BSL entry sequence detected 1b BSL entry sequence detected 3 Reserved R 0h Reserved Always reads as 0 2 SYSPMMPE RW 0h PMM access protect This controls the accessibility of the PMM control registers Once set to 1 it only can b...

Page 56: ...ge is written to the upper byte of JMBO1 or as word access by the CPU DMA and is set after the message was read via JTAG 0b JMBO1 is not ready to receive new data 1b JMBO1 is ready to receive new data 2 JMBOUT0FG R 1h Outgoing JTAG Mailbox 0 flag This bit is cleared automatically when a message is written to the upper byte of JMBO0 or as word access by the CPU DMA and is set after the message was ...

Page 57: ...essage low byte 1 16 4 SYSJMBI1 Register JTAG Mailbox Input 1 Register Figure 1 13 SYSJMBI1 Register 15 14 13 12 11 10 9 8 MSGHI rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 MSGLO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 1 19 SYSJMBI1 Register Description Bit Field Type Reset Description 15 8 MSGHI RW 0h JTAG mailbox incoming message high byte 7 0 MSGLO RW 0h JTAG mailbox incoming ...

Page 58: ...essage low byte 1 16 6 SYSJMBO1 Register JTAG Mailbox Output 1 Register Figure 1 15 SYSJMBO1 Register 15 14 13 12 11 10 9 8 MSGHI rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 MSGLO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 1 21 SYSJMBO1 Register Description Bit Field Type Reset Description 15 8 MSGHI RW 0h JTAG mailbox outgoing message high byte 7 0 MSGLO RW 0h JTAG mailbox outgoing...

Page 59: ...st of values 1 16 8 SYSSNIV Register System NMI Vector Register Figure 1 17 SYSSNIV Register 15 14 13 12 11 10 9 8 SYSSNIV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 SYSSNIV r0 r0 r0 r 0 r 0 r 0 r 0 r0 Table 1 23 SYSSNIV Register Description Bit Field Type Reset Description 15 0 SYSSNIV R 0h System NMI vector Generates a value that can be used as address offset for fast interrupt service routine hand...

Page 60: ...SRSTIV R 02h Reset interrupt vector Generates a value that can be used as address offset for 03Eh 1 fast interrupt service routine handling to identify the last cause of a reset BOR POR PUC Writing to this register clears all pending reset source flags See the device specific data sheet for a list of values 1 Reset value depends on reset source 60 System Resets Interrupts and Operating Modes Syste...

Page 61: ... the Power Management Module PMM and Supply Voltage Supervisor SVS Topic Page 2 1 Power Management Module PMM Introduction 62 2 2 PMM Operation 63 2 3 PMM Registers 66 61 SLAU272C May 2011 Revised November 2013 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 62: ...oth the voltage applied to the device DVCC and the voltage generated for the core VCORE The PMM uses an integrated low dropout voltage regulator LDO to produce a secondary core voltage VCORE from the primary one applied to the device DVCC In general VCORE supplies the CPU memories and the digital modules while DVCC supplies the I Os and analog modules The VCORE output is maintained using a dedicat...

Page 63: ... Supervisor The high side supervisor SVSH and the low side supervisor SVSL oversee DVCC and VCORE respectively The high side supervisor SVSH is always active in all power modes It can be disabled only in LPM4 5 with SVSHE 0 By default the low side supervisor SVSL is enabled in active mode LPM0 LPM1 and LPM2 It can be disabled in LPM1 and LPM2 with SVSLE 0 The SVSL is always disabled in LPM3 LPM3 5...

Page 64: ... Reset BOR The primary function of the brownout reset BOR circuit occurs when the device is powering up It is functional very early in the power up ramp generating a BOR that initializes the system It also functions when no SVS is enabled and a brownout condition occurs It sustains this reset until the input power is sufficient for the logic to enable proper reset of the system In an application i...

Page 65: ...ans of ensuring that I O pins cannot behave in uncontrolled fashion during an undervoltage event During these times outputs are disabled both normal drive and the weak pullup or pulldown function If the CPU is functioning normally and then an undervoltage event occurs any pin configured as an input has its PxIN register value locked when the event occurs until voltage is restored During the underv...

Page 66: ...a PUC NOTE All registers have word or byte register access For a generic register ANYREG the suffix _L ANYREG_L refers to the lower byte of the register bits 0 through 7 The suffix _H ANYREG_H refers to the upper byte of the register bits 8 through 15 Table 2 1 PMM Registers Offset Acronym Register Name Type Access Reset Section 00h PMMCTL0 PMM control register 0 Read write Word 9660h Section 2 3 ...

Page 67: ...nabled in active mode and LPM0 LPM1 LPM2 LPM3 LPM4 and LPM3 5 1b SVSH is always enabled 5 SVSLE RW 1h Low side SVS enable 0b Low side SVS SVSL is disabled in low power modes SVSL is always enabled in active mode and LPM0 1b SVSL is enabled in LPM0 LPM1 and LPM2 SVSL is always enabled in AM and always disabled in LPM3 LPM4 LPM3 5 and LPM4 5 4 PMMREGOFF RW 0h Regulator off 0b Regulator remains on wh...

Page 68: ...ue to SVSH 1b Reset due to SVSH 12 SVSLIFG RW 0h Low side SVS interrupt flag This interrupt flag is only set if the SVSL is the reset source that is if the core voltage dropped below the low side SVS levels but DVCC remained above the SVSH levels The bit is cleared by software or by reading the reset vector word 0b Reset not due to SVSL 1b Reset due to SVSL 11 Reserved R 0h Reserved Always reads a...

Page 69: ...h Reserved Always reads as 0 0 LOCKLPM5 RW 0h Lock I O pin and other LPMx 5 relevant for example RTC configurations upon entry to or exit from LPMx 5 When power is applied to the device and this bit is set the bit can only be cleared by the user or by another power cycle 0b LPMx 5 configuration is not locked and defaults to its reset condition 1b LPMx 5 configuration remains locked Pin state is he...

Page 70: ...lock system which is implemented in all devices Topic Page 3 1 Clock System Introduction 71 3 2 Clock System Operation 73 3 3 Module Oscillator MODOSC 78 3 4 CS Registers 79 70 Clock System CS SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 71: ... controlled oscillator DCO with three selectable fixed frequencies XT2CLK Optional high frequency oscillator that can be used with standard crystals resonators or external clock sources in the 4 MHz to 24 MHz range See the device specific data sheet for availability Four system clock signals are available from the clock module ACLK Auxiliary clock The ACLK is software selectable as XT1CLK VLOCLK D...

Page 72: ...0 001 010 011 100 101 110 111 SELS SMCLK 1 0 3 Divider DIVS EN 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 VLOCLK VLO XT2CLK XT2 XT2IN XT2OUT XT2DRIVE XT2BYPASS XT2 Fault Detection 0 1 1 0 XT1CLK XIN XOUT LF XT1DRIVE XT1BYPASS XT1 Fault Detection 0 1 1 0 HF XTS XT1 2 2 XT1CLK Optional module 1 0 5 3 6 7 8 MHz 16 20 24 MHz DCOFSEL 2 Not available on all devices Clock System Introduction www ti com Fi...

Page 73: ...g requirements by allowing the user to select from the three available clock signals ACLK MCLK and SMCLK All three available clock signals can be sourced from any of the available clock sources XT1CLK VLOCLK DCOCLK or XT2CLK giving complete flexibility in the system clock configuration A flexible clock distribution and divider system is provided to fine tune the individual clock requirements 3 2 2...

Page 74: ... shared with general purpose I O ports At power up the default operation is XT2 However XT2 remains disabled until the ports shared with XT2 are configured for XT2 operation The configuration of the shared I O is determined by the PSEL bit associated with XT2IN and the XT2BYPASS bit Setting the PSEL bit causes the XT2IN and XT2OUT ports to be configured for XT2 operation If XT2BYPASS is also set X...

Page 75: ...or example a peripheral module may require ACLK that is currently disabled by the OSCOFF bit OSCOFF 1 The module can request ACLK by generating an ACLK_REQ This causes the OSCOFF bit to have no effect thereby allowing ACLK to be available to the requesting peripheral module The OSCOFF bit remains at its current setting OSCOFF 1 If the requested source is not active the software NMI handler must ma...

Page 76: ...ault fail safe feature This feature detects an oscillator fault for XT1 and XT2 as shown in Figure 3 3 The available fault conditions are Low frequency oscillator fault XT1OFFG for XT1 in LF mode High frequency oscillator fault XT1OFFG for XT1 in HF mode High frequency oscillator fault XT2OFFG for XT2 External clock signal faults for all bypass modes that is XT1BYPASS 1 or XT2BYPASS 1 The crystal ...

Page 77: ...d after operation resumes The fault condition causes XT1OFFG to be set and remain set If the user clears XT1OFFG and the fault condition still exists XT1OFFG remains set XT2_OscFault This signal is set after the XT2 oscillator has stopped operation and is cleared after operation resumes The fault condition causes XT2OFFG to be set and remain set If the user clears XT2OFFG and the fault condition s...

Page 78: ... high period Figure 3 4 Switch MCLK from DCOCLK to XT1CLK 3 3 Module Oscillator MODOSC The CS module also supports an internal oscillator MODOSC that is used by the power management module and optionally by other modules in the system It is also used as a fail safe clock source as described in Section 3 2 7 The MODOSC sources MODCLK 3 3 1 MODOSC Operation To conserve power MODOSC is powered down w...

Page 79: ...Section 3 4 1 00h CSCTL0_L Read write Byte 00h 01h CSCTL0_H Read write Byte 96h 02h CSCTL1 Clock System Control 1 Read write Word 0007h Section 3 4 2 02h CSCTL1_L Read write Byte 07h 03h CSCTL1_H Read write Byte 00h 04h CSCTL2 Clock System Control 2 Read write Word 0033h Section 3 4 3 04h CSCTL2_L Read write Byte 33h 05h CSCTL2_H Read write Byte 00h 06h CSCTL3 Clock System Control 3 Read write Wor...

Page 80: ...15 8 CSKEY RW 96h CSKEY password Always reads as 096h Must be written as 0A5h when writing in word mode writing any other value in word mode generates a PUC After a correct password is written and CS register accesses are enabled a wrong password write in byte mode disables the access and no PUC is generated 7 0 Reserved R 0h Reserved Always reads as 0 80 Clock System CS SLAU272C May 2011 Revised ...

Page 81: ...ORSEL RW 0h DCO range select For high speed devices this bit can be written by the user For low speed devices it is always reset See DCOFSEL for valid values 6 3 Reserved R 0h Reserved Always reads as 0 2 1 DCOFSEL RW 3h DCO frequency select For some devices DCORSEL 1 setting is not available If DCORSEL 0 00b 5 33 01b 6 67 10b 5 33 11b 8 If DCORSEL 1 00b 16 01b 20 10b 16 11b 24 0 Reserved R 1h Res...

Page 82: ...herwise DCOCLK 7 Reserved R 0h Reserved Always reads as 0 6 4 SELS RW 3h Selects the SMCLK source 000b XT1CLK 001b VLOCLK 010b Reserved Defaults to VLOCLK 011b DCOCLK 100b Reserved Defaults to DCOCLK 101b XT2CLK when available otherwise DCOCLK 110b Reserved Defaults to XT2CLK when available otherwise DCOCLK 111b Reserved Defaults to XT2CLK when available otherwise DCOCLK 3 Reserved R 0h Reserved A...

Page 83: ...o f ACLK 32 111b Reserved Defaults to f ACLK 32 7 Reserved R 0h Reserved Always reads as 0 6 4 DIVS RW 3h SMCLK source divider Divides the frequency of the SMCLK clock source 000b f SMCLK 1 001b f SMCLK 2 010b f SMCLK 4 011b f SMCLK 8 100b f SMCLK 16 101b f SMCLK 32 110b Reserved Defaults to f SMCLK 32 111b Reserved Defaults to f SMCLK 32 3 Reserved R 0h Reserved Always reads as 0 2 0 DIVM RW 3h M...

Page 84: ...ed by the port selection and XT2 is not in bypass mode of operation 1b XT2 is off if it is not used as a source for ACLK MCLK or SMCLK 7 6 XT1DRIVE RW 3h The XT1 oscillator current can be adjusted to its drive needs 00b Lowest current consumption for XT1 LF mode XT1 oscillator operating range in HF mode is 4 MHz to 8 MHz 01b Increased drive strength for XT1 LF mode XT1 oscillator operating range i...

Page 85: ...d R 0h Reserved Always reads as 0 1 XT2OFFG RW 0h XT2 oscillator fault flag If this bit is set the OFIFG flag is also set XT2OFFG is set if a XT2 fault condition exists XT2OFFG can be cleared by software If the XT2 fault condition still remains XT2OFFG is set On devices without XT2 this flag is read only zero 0b No fault condition occurred after the last reset 1b XT2 fault An XT2 fault occurred af...

Page 86: ...DCLK conditional requests are enabled 2 SMCLKREQEN RW 1h SMCLK clock request enable Setting this enables conditional module requests for SMCLK 0b SMCLK conditional requests are disabled 1b SMCLK conditional requests are enabled 1 MCLKREQEN RW 1h MCLK clock request enable Setting this enables conditional module requests for MCLK 0b MCLK conditional requests are disabled 1b MCLK conditional requests...

Page 87: ...ally called CPUXV2 has in some cases slightly different cycle counts from the MSP430X CPUX implemented on the 2xx and 4xx families Topic Page 4 1 MSP430X CPU CPUX Introduction 88 4 2 Interrupts 90 4 3 CPU Registers 91 4 4 Addressing Modes 97 4 5 MSP430 and MSP430X Instructions 114 4 6 Instruction Set Description 130 87 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copy...

Page 88: ...rogram counter PC status register SR and stack pointer SP Single cycle register operations Large register file reduces fetches to memory 20 bit address bus allows direct access and branching throughout the entire memory range without paging 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides the six most often used immediate values and reduces code size Di...

Page 89: ...General Purpose General Purpose General Purpose General Purpose General Purpose Memory Address Bus MAB MDB Memor y Data Bus 16 20 16 20 bit ALU src dst Zero Z Carry C Overflow V Negative N MCLK 0 16 15 R2 SR Status Register www ti com MSP430X CPU CPUX Introduction Figure 4 1 MSP430X CPU Block Diagram 89 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 ...

Page 90: ...During an interrupt the program counter PC and the status register SR are pushed onto the stack as shown in Figure 4 2 The MSP430X architecture stores the complete 20 bit PC value efficiently by appending the PC bits 19 16 to the stored SR value automatically on the stack When the RETI instruction is executed the full 20 bit PC is restored making return from interrupt to any address in the memory ...

Page 91: ...ith the BR or CALL instruction When branching or calling addresses beyond the lower 64 KB range can only be reached using the BRA or CALLA instructions Also any instruction to directly modify the PC does so according to the used addressing mode For example MOV W value PC clears the upper four bits of the PC because it is a W instruction The PC is automatically stored on the stack with CALL or CALL...

Page 92: ... W 2 SP R6 Copy Item I2 to R6 MOV W R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h on stack POP R8 R8 0123h CPU Registers www ti com Figure 4 6 shows the stack usage Figure 4 7 shows the stack usage when 20 bit address words are pushed Figure 4 5 Stack Pointer Figure 4 6 Stack Usage Figure 4 7 PUSHX A Format on the Stack The special cases of using the SP as an argument to the PUSH and POP inst...

Page 93: ...ctions in the clock system depending on the device family for example DCO bias enable or disable SCG0 System clock generator 0 This bit may be used to enable or disable functions in the clock system depending on the device family for example FLL enable or disable OSCOFF Oscillator off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or SMCLK CPUOFF CPU of...

Page 94: ...ditional code word for the six constants No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers 4 3 4 1 Constant Generator Expanded Instruction Set The RISC instruct...

Page 95: ...rough the complete 20 bit register Figure 4 10 through Figure 4 14 show the handling of byte word and address word data Note the reset of the leading most significant bits MSBs if a register is the destination of a byte or word instruction Figure 4 10 shows byte handling 8 bit data B suffix The handling is shown for a source register and a destination memory byte and for a source memory byte and a...

Page 96: ...ters www ti com Figure 4 12 Word Register Operation Figure 4 13 and Figure 4 14 show 20 bit address word handling A suffix The handling is shown for a source register and a destination memory address word and for a source memory address word and a destination register Figure 4 13 Register Address Word Operation 96 CPUX SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright...

Page 97: ...owing the instruction contains the absolute address X is stored in the next word or stored in combination of the preceding extension word and the next word Indexed mode X SR is used 10 Indirect Register Rn Rn is used as a pointer to the operand 11 Indirect Rn Rn is used as a pointer to the operand Rn is incremented afterwards by 1 for B Autoincrement instructions by 2 for W instructions and by 4 f...

Page 98: ...tion reads the 16 LSBs of the source register Rsrc and writes the result to the 16 LSBs of the destination register Rdst The bits Rdst 19 16 are cleared The register Rsrc is not modified Address word Address word operation reads the 20 bits of the source register Rsrc and writes the operation result to the 20 bits of the destination register Rdst The register Rsrc is not modified SXT exception The...

Page 99: ...e is usable without modifications as shown in Figure 4 15 Figure 4 15 Indexed Mode in Lower 64 KB Length Two or three words Operation The signed 16 bit index is located in the next word after the instruction and is added to the CPU register Rn The resulting bits 19 16 are cleared giving a truncated 16 bit memory address which points to an operand address in the range 00000h to 0FFFFh The operand i...

Page 100: ...um 0479Ch 1000h 0579Ch xxxxh xx32h 0579Eh 0579Ch xxxxh xx32h 0579Eh 0579Ch Addressing Modes www ti com 4 4 2 2 MSP430 Instruction With Indexed Mode in Upper Memory If the CPU register Rn points to an address above the lower 64 KB memory the Rn bits 19 16 are used for the address calculation of the operand The operand may be located in memory in the range Rn 32 KB because the index X is a signed 16...

Page 101: ...for source and destination The assembler calculates the register index and inserts it ADD W 8346h R5 2100h R6 Example This instruction adds the 16 bit data contained in the source and the destination addresses and places the 16 bit result into the destination Source and destination operand can be located in the entire address range Source The word pointed to by R5 8346h The negative index 8346h is...

Page 102: ...ords Operation The operand address is the sum of the 20 bit CPU register content and the 20 bit index The 4 MSBs of the index are contained in the extension word the 16 LSBs are contained in the word following the instruction The CPU register is not modified Comment Valid for source and destination The assembler calculates the register index and inserts it ADDX A 12346h R5 32100h R6 Example This i...

Page 103: ... of the operand by adding the signed index to the PC The Symbolic mode has three addressing possibilities Symbolic mode in lower 64 KB memory MSP430 instruction with Symbolic mode addressing memory above the lower 64 KB memory MSP430X instruction with Symbolic mode 4 4 3 1 Symbolic Mode in Lower 64 KB If the PC points to an address in the lower 64 KB of the memory range the calculated memory addre...

Page 104: ...ce and destination The assembler calculates the PC index and inserts it ADD B EDE TONI Example This instruction adds the 8 bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI Bytes EDE and TONI and the program are located in the lower 64 KB Source Byte EDE located at address 0579Ch pointed to by PC 4766h where the PC index 4766h is t...

Page 105: ... xx32h 0579Eh 0579Ch xxxxh xx32h 0579Eh 0579Ch www ti com Addressing Modes 4 4 3 2 MSP430 Instruction With Symbolic Mode in Upper Memory If the PC points to an address above the lower 64 KB memory the PC bits 19 16 are used for the address calculation of the operand The operand may be located in memory in the range PC 32 KB because the index X is a signed 16 bit value In this case the address of t...

Page 106: ...ion The assembler calculates the PC index and inserts it ADD W EDE TONI Example This instruction adds the 16 bit data contained in source word EDE and destination word TONI and places the 16 bit result into the destination word TONI For this example the instruction is located at address 2F034h Source Word EDE at address 3379Ch pointed to by PC 4766h which is the 16 bit result of 3379Ch 2F036h 0476...

Page 107: ...ained in the extension word the 16 LSBs are contained in the word following the instruction Comment Valid for source and destination The assembler calculates the register index and inserts it ADDX B EDE TONI Example This instruction adds the 8 bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI Source Byte EDE located at address 3579...

Page 108: ...bsolute addressing mode the absolute address is a 16 bit value and therefore points to an address in the lower 64 KB of the memory range The address is calculated as an index from 0 and is stored in the word following the instruction The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications Length Two or three words Operation The ope...

Page 109: ... calculated as an index from 0 The 4 MSBs of the index are contained in the extension word and the 16 LSBs are contained in the word following the instruction Length Three or four words Operation The operand is the content of the addressed memory location Comment Valid for source and destination The assembler calculates the index from 0 and inserts it ADDX A EDE TONI Example This instruction adds ...

Page 110: ... 20 bit address Length One two or three words Operation The operand is the content the addressed memory location The source register Rsrc is not modified Comment Valid only for the source operand The substitute for the destination operand is 0 Rdst ADDX W R5 2100h R6 Example This instruction adds the two 16 bit operands contained in the source and the destination addresses and places the result in...

Page 111: ... instructions immediately after accessing the source operand If the same register is used for source and destination it contains the incremented address for the destination access Indirect Autoincrement mode always uses 20 bit addresses Length One two or three words Operation The operand is the content of the addressed memory location Comment Valid only for the source operand ADD B R5 0 R6 Example...

Page 112: ...ructions The Immediate mode has two addressing possibilities 8 bit or 16 bit constants with MSP430 instructions 20 bit constants with MSP430X instruction 4 4 7 1 MSP430 Instructions With Immediate Mode If an MSP430 instruction is used with Immediate addressing mode the constant is an 8 or 16 bit value and is stored in the word following the instruction Length Two or three words One word less if a ...

Page 113: ...with Immediate addressing mode the constant is a 20 bit value The 4 MSBs of the constant are stored in the extension word and the 16 LSBs of the constant are stored in the word following the instruction Length Three or four words One word less if a constant of the constant generator can be used for the immediate operand Operation The 20 bit immediate source operand is used together with the 20 bit...

Page 114: ...o reach addresses within the range of PC 32 KB To use only MSP430X instructions The disadvantages of this method are the reduced speed due to the additional CPU cycles and the increased program space due to the necessary extension word for any double operand instruction Use the best fitting instruction where needed Section 4 5 1 lists and describes the MSP430 instructions and Section 4 5 2 lists a...

Page 115: ...nd Format II Instructions Figure 4 23 shows the format for MSP430 single operand instructions except RETI The destination word is appended for the Indexed Symbolic Absolute and Immediate modes Table 4 5 lists the seven single operand instructions Figure 4 23 MSP430 Single Operand Instructions Table 4 5 MSP430 Single Operand Instructions Status Bits 1 S Reg Mnemonic Operation D Reg V N Z C dst C MS...

Page 116: ... 5 1 4 Emulated Instructions In addition to the MSP430 and MSP430X instructions emulated instructions are instructions that make code easier to write and read but do not have op codes themselves Instead they are replaced automatically by the assembler with a core instruction There is no code or performance penalty for using emulated instructions The emulated instructions are listed in Table 4 7 Ta...

Page 117: ... 5 1 Instruction Cycles and Length for Interrupt Reset and Subroutines Table 4 8 lists the length and the CPU cycles for reset interrupts and subroutines Table 4 8 Interrupt Return and Reset Cycles and Length Execution Time Length of Instruction Action MCLK Cycles Words Return from interrupt RETI 5 1 Return from subroutine RET 4 1 Interrupt request service cycles needed before first 6 instruction ...

Page 118: ...DE Rn Rm 2 1 AND R4 R5 PC 4 1 BR R8 x Rm 5 1 2 XOR R5 8 R6 EDE 5 1 2 MOV R5 EDE EDE 5 1 2 XOR R5 EDE Rn Rm 2 1 ADD R5 R6 PC 4 1 BR R9 x Rm 5 1 2 XOR R5 8 R6 EDE 5 1 2 MOV R9 EDE EDE 5 1 2 MOV R9 EDE N Rm 2 2 MOV 20 R9 PC 3 2 BR 2AEh x Rm 5 1 3 MOV 0300h 0 SP EDE 5 1 3 ADD 33 EDE EDE 5 1 3 ADD 33 EDE x Rn Rm 3 2 MOV 2 R5 R7 PC 5 2 BR 2 R6 TONI 6 1 3 MOV 4 R7 TONI x Rm 6 1 3 ADD 4 R4 6 R9 TONI 6 1 3...

Page 119: ...11 Extension word op code Op codes 1800h to 1FFFh are extension words 10 9 Reserved ZC Zero carry 0 The executed instruction uses the status of the carry bit C 1 The executed instruction uses the carry bit as 0 The carry bit is defined by the result of the final operation after instruction execution Repetition 0 The number of instruction repetitions is set by extension word bits 3 0 1 The number o...

Page 120: ...SBs may belong to an 19 16 immediate operand an index or to an absolute address A L Data length extension Together with the B W bits of the following MSP430 instruction the AL bit defines the used data length of the instruction A L B W Comment 0 0 Reserved 0 1 20 bit address word 1 0 16 bit word 1 1 8 bit byte 5 4 Reserved Destination The four MSBs of the 20 bit destination Depending on the destin...

Page 121: ... as listed in Table 4 13 Table 4 13 Extended Double Operand Instructions Status Bits 1 Mnemonic Operands Operation V N Z C src dst src dst MOVX B A src dst src dst dst ADDX B A src dst src dst C dst ADDCX B A src dst dst not src 1 dst SUBX B A src dst dst not src C dst SUBCX B A src dst dst src CMPX B A src dst src dst C dst decimal DADDX B A src dst src and dst 0 Z BITX B A src dst not src and ds...

Page 122: ... 0 0 As src 19 16 As dst 15 0 MSP430 and MSP430X Instructions www ti com The four possible addressing combinations for the extension word for Format I instructions are shown in Figure 4 29 Figure 4 29 Extended Format I Instruction Formats If the 20 bit address of a source or destination operand is located in memory not in a CPU register then two words are used for this operand as shown in Figure 4...

Page 123: ... PUSHX B A n Rdst Rotate right Rdst n bits through carry 16 20 bit register 1 to 4 0 RRCM A n Rdst Rotate right Rdst n bits unsigned 16 20 bit register 1 to 4 0 RRUM A n Rdst Rotate right Rdst n bits arithmetically 16 20 bit register 1 to 4 0 RRAM A n Rdst Rotate left Rdst n bits arithmetically 16 20 bit register 1 to 4 RLAM A dst Rotate right dst through carry 8 16 20 bit data 1 0 RRCX B A Rdst R...

Page 124: ...nd MSP430X Instructions www ti com 4 5 2 4 1 Extended Format II Instruction Format Exceptions Exceptions for the Format II instruction formats are shown in Figure 4 32 through Figure 4 35 Figure 4 32 PUSHM and POPM Instruction Format Figure 4 33 RRCM RRAM RRUM and RLAM Instruction Format Figure 4 34 BRA Instruction Format Figure 4 35 CALLA Instruction Format 124 CPUX SLAU272C May 2011 Revised Nove...

Page 125: ...crement dst by 1 DECX B A dst SUBX B A 1 dst Decrement Rdst by 2 DECDA Rdst SUBA 2 Rdst Decrement dst by 2 DECDX B A dst SUBX B A 2 dst Increment dst by 1 INCX B A dst ADDX B A 1 dst Increment Rdst by 2 INCDA Rdst ADDA 2 Rdst Increment dst by 2 INCDX B A dst ADDX B A 2 dst Invert dst INVX B A dst XORX B A 1 dst Shift left dst arithmetically RLAX B A dst ADDX B A dst dst Shift left dst logically th...

Page 126: ...on is needed with the corresponding restricted addressing mode Table 4 16 Address Instructions Operate on 20 Bit Register Data Status Bits 1 Mnemonic Operands Operation V N Z C Add source to destination register ADDA Rsrc Rdst imm20 Rdst Move source to destination MOVA Rsrc Rdst imm20 Rdst z16 Rsrc Rdst EDE Rdst abs20 Rdst Rsrc Rdst Rsrc Rdst Rsrc z16 Rdst Rsrc abs20 Compare source to destination ...

Page 127: ...ns Table 4 17 MSP430X Format II Instruction Cycles and Length Execution Cycles Length of Instruction Words Instruction Rn Rn Rn N X Rn EDE EDE RRAM n 1 RRCM n 1 RRUM n 1 RLAM n 1 PUSHM 2 n 1 PUSHM A 2 2n 1 POPM 2 n 1 POPM A 2 2n 1 CALLA 5 1 6 1 6 1 5 2 5 1 2 7 2 7 2 RRAX B 1 n 2 4 2 4 2 5 3 5 3 5 3 RRAX A 1 n 2 6 2 6 2 7 3 7 3 7 3 RRCX B 1 n 2 4 2 4 2 5 3 5 3 5 3 RRCX A 1 n 2 6 2 6 2 7 3 7 3 7 3 P...

Page 128: ...TX 20 R8 PC 4 4 4 3 ADDX A FE000h PC x Rm 6 2 8 3 4 ANDX 1234 4 R6 EDE 6 2 8 3 4 XORX A5A5h EDE EDE 6 2 8 3 4 BITX B 12 EDE x Rn Rm 4 5 3 BITX 2 R5 R8 PC 4 6 7 3 SUBX A 2 R6 PC TONI 7 2 10 3 4 ANDX 4 R7 4 R6 x Rm 7 2 10 3 4 XORX B 2 R6 EDE TONI 7 2 10 3 4 BITX 8 SP EDE EDE Rm 4 5 3 BITX B EDE R8 PC 4 6 7 3 ADDX A EDE PC TONI 7 2 10 3 4 ANDX EDE 4 R6 x Rm 7 2 10 3 4 ANDX EDE TONI TONI 7 2 10 3 4 BI...

Page 129: ...MOVA Source Destination ADDA MOVA ADDA BRA SUBA SUBA Rn Rn 1 1 1 1 CMPA R5 R8 PC 3 3 1 1 SUBA R9 PC x Rm 4 2 MOVA R5 4 R6 EDE 4 2 MOVA R8 EDE EDE 4 2 MOVA R5 EDE Rn Rm 3 1 MOVA R5 R8 PC 5 1 MOVA R9 PC Rn Rm 3 1 MOVA R5 R8 PC 5 1 MOVA R9 PC N Rm 2 3 2 2 CMPA 20 R8 PC 3 3 2 2 SUBA FE000h PC x Rn Rm 4 2 MOVA 2 R5 R8 PC 6 2 MOVA 2 R6 PC EDE Rm 4 2 MOVA EDE R8 PC 6 2 MOVA EDE PC EDE Rm 4 2 MOVA EDE R8 ...

Page 130: ...RETI B B B H H B A 14xx PUSHM A POPM A PUSHM W POPM W 18xx Extension word for Format I and Format II instructions 1Cxx 20xx JNE JNZ 24xx JEQ JZ 28xx JNC 2Cxx JC 30xx JN 34xx JGE 38xx JL 3Cxx JMP 4xxx MOV MOV B 5xxx ADD ADD B 6xxx ADDC ADDC B 7xxx SUBC SUBC B 8xxx SUB SUB B 9xxx CMP CMP B Axxx DADD DADD B Bxxx BIT BIT B Cxxx BIC BIC B Dxxx BIS BIS B Exxx XOR XOR B Fxxx AND AND B 130 CPUX SLAU272C M...

Page 131: ... 0 0 imm 19 16 1 0 1 0 dst ADDA imm20 Rdst imm 15 0 SUBA 0 0 0 0 imm 19 16 1 0 1 1 dst SUBA imm20 Rdst imm 15 0 MOVA 0 0 0 0 src 1 1 0 0 dst MOVA Rsrc Rdst CMPA 0 0 0 0 src 1 1 0 1 dst CMPA Rsrc Rdst ADDA 0 0 0 0 src 1 1 1 0 dst ADDA Rsrc Rdst SUBA 0 0 0 0 src 1 1 1 1 dst SUBA Rsrc Rdst Instruction Instruction Bit Loc Inst ID dst Group Identifier Instruction 15 12 11 10 9 8 7 4 3 0 RRCM A 0 0 0 0 ...

Page 132: ...16 CALLA abs20 abs 15 0 0 0 0 1 0 0 1 1 1 0 0 1 x 19 16 CALLA EDE x 15 0 CALLA x PC 0 0 0 1 0 0 1 1 1 0 1 1 imm 19 16 CALLA imm20 imm 15 0 Reserved 0 0 0 1 0 0 1 1 1 0 1 0 x x x x Reserved 0 0 0 1 0 0 1 1 1 1 x x x x x x PUSHM A 0 0 0 1 0 1 0 0 n 1 dst PUSHM A n Rdst PUSHM W 0 0 0 1 0 1 0 1 n 1 dst PUSHM W n Rdst POPM A 0 0 0 1 0 1 1 0 n 1 dst n 1 POPM A n Rdst POPM W 0 0 0 1 0 1 1 1 n 1 dst n 1 P...

Page 133: ...iption 4 6 2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages 133 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 134: ...was incremented from 0FFFFh to 0000 reset otherwise Set if dst was incremented from 0FFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD Example The 8 bit counter pointed to by R13...

Page 135: ...gative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Ten is added to the 16 bit counter CNTR located in lower 64 K ADD W 10 CNTR Add 10 to 16 bit counter Example A table word pointed to by R5 20 bit address in R5 is added to R6 The jump to label TONI is performed on a carry ADD W R5 R6 Add table word to R6 R6 19 16 0 JC TONI Jump if carry No carry Exa...

Page 136: ...itive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Constant value 15 and the carry of the previous instruction are added to the 16 bit counter CNTR located in lower 64 K ADDC W 15 CNTR Add 15 C to 16 bit CNTR Example A table word pointed to by R5 20 bit address and the carry C are added to R6 The jump to label TONI is performed on a carry R6 19 16 0 ADDC W R5 R6 Add tab...

Page 137: ...ro reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits set in R5 16 bit data are used as a mask AA55h for the word TOM located in the lower 64 K If the result is zero a branch is taken to label TONI R5 19 16 0 MOV AA55h R5 Load 16 bit mask to R5 AND R5 TOM TOM and R5 TOM JZ TONI Jump if result 0 Result 0 or shorter AND AA55h TOM TOM and AA55h TOM JZ TO...

Page 138: ...tatus Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits 15 14 of R5 16 bit data are cleared R5 19 16 0 BIC 0C000h R5 Clear R5 19 14 bits Example A table word pointed to by R5 20 bit address is used to clear bits in R7 R7 19 16 0 BIC W R5 R7 Clear bits in R7 set in R5 Example A table byte pointed to by R5 20 bit addres...

Page 139: ... Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Bits 15 and 13 of R5 16 bit data are set to one R5 19 16 0 BIS A000h R5 Set R5 bits Example A table word pointed to by R5 20 bit address is used to set bits in R7 R7 19 16 0 BIS W R5 R7 Set bits in R7 Example A table byte pointed to by R5 20 bit address is used to set bits in Port1 R...

Page 140: ...ffected Example Test if one or both of bits 15 and 14 of R5 16 bit data is set Jump to label TONI if this is the case R5 19 16 are not affected BIT C000h R5 Test R5 15 14 bits JNZ TONI At least one bit is set in R5 Both bits are reset Example A table word pointed to by R5 20 bit address is used to test bits in R7 Jump to label TONI if at least one bit is set R7 19 16 are not affected BIT W R5 R7 T...

Page 141: ...ress EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards The next time S W flow uses R5 pointer it...

Page 142: ...e given Immediate Mode Call a subroutine at label EXEC lower 64 K or call directly to address CALL EXEC Start address EXEC CALL 0AA04h Start address 0AA04h Symbolic Mode Call a subroutine at the 16 bit address contained in address EXEC EXEC is located at the address PC X where X is within PC 32 K CALL EXEC Start address at EXEC z16 PC Absolute Mode Call a subroutine at the 16 bit address contained...

Page 143: ...ion MOV B 0 dst Description The destination operand is cleared Status Bits Status bits are not affected Example RAM word TONI is cleared CLR TONI 0 TONI Example Register R5 is cleared CLR R5 Example RAM byte TONI is cleared CLR B TONI 0 TONI 143 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 144: ...cted C Cleared V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter 144 CPUX SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Cop...

Page 145: ...gative bit instruction is a word instruction Status Bits N Reset to 0 Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The negative bit in the SR is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR SUBR JN SUBRET If input is negative do nothing and return SUBRET RET 145 SLAU272C May 2011 Revised...

Page 146: ...Call a subroutine at the 16 bit address contained in the word pointed to by register R5 20 bit address and increment the 16 bit address in R5 afterwards by 2 The next time the software uses R5 as a pointer it can alter the program execution due to access to the next word address in the table pointed to by R5 CALL R5 Start address at R5 R5 2 Indexed mode Call a subroutine at the 16 bit address cont...

Page 147: ... a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example Compare word EDE with a 16 bit constant 1800h Jump to label TONI if EDE equals the constant The address of EDE is within PC 32 K CMP 01800h EDE Compare word EDE with 1800h JEQ TONI EDE contains 1800h Not equal Example A table...

Page 148: ...om 99 to 00 reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The four digit decimal number contained in R5 is added to an eight digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD Example The two digit decimal number contained in R5 is added to a four digit decima...

Page 149: ...lt is too large word 9999h byte 99h reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example Decimal 10 is added to the 16 bit BCD counter DECCNTR DADD 10h DECCNTR Add 10 to 4 digit BCD counter Example The eight digit BCD number contained in 16 bit RAM addresses BCD and BCD 2 is added decimally to an eight digit BCD number contained in R4 and R5 BCD 2 and R5 contain the...

Page 150: ...ue of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range...

Page 151: ... 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the ra...

Page 152: ...e protected from interruption DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or it should be followed by a NOP instruction NOTE Enable and Disable Interrupt Due to the pipelined CPU architecture the instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts...

Page 153: ...on at the start of interrupt subroutine Corrects the stack pointer RETI NOTE Enable and Disable Interrupt Due to the pipelined CPU architecture the instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enabled If the enable interrupt instruction EINT is immediately followed by a disable interrupt instr...

Page 154: ...Fh reset otherwise Set if dst contained 0FFh reset otherwise C Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The status byte STATUS of a process is incremented When it is equal to 11 a branch to OVFL is taken INC B ...

Page 155: ...t if dst contained 0FEh or 0FFh reset otherwise V Set if dst contained 07FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment...

Page 156: ...ned 0FFh reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example Content of R5 is negated 2s complement MOV 00AEh R5 R5 000AEh INV R5 Invert R5 R5 0FF51h INC R5 R5 is now negated R5 0FF52h Example Content of memory byte LEO is negated MOV B 0AEh LEO MEM LEO 0AEh I...

Page 157: ...d for the test of the carry bit C JHS is used for the comparison of unsigned numbers Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The state of the port 1 pin P1IN 1 bit defines the program flow BIT B 2 P1IN Port 1 bit 1 set Bit C JC Label1 Yes proceed at Label1 No continue Example If R5 R6 unsigned the program continues at Label2 CMP R6 R 5 Is R...

Page 158: ... Z JEQ is used for the comparison of operands Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The state of the P2IN 0 bit defines the program flow BIT B 1 P2IN Port 2 bit 0 reset JZ Label1 Yes proceed at Label1 No set continue Example If R5 15000h 20 bit data the program continues at Label2 CMPA 15000h R5 Is R5 15000h Info to SR JEQ Label2 Yes R5 1...

Page 159: ...onimplemented JP jump if positive instruction if used after the instructions AND BIT RRA SXTX and TST These instructions clear the V bit Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example If byte EDE lower 64 K contains positive data go to Label1 Software can run in the full memory range TST B EDE Is EDE positive V 0 JGE Label1 Yes JGE emulates JP No ...

Page 160: ... the decision made by the JL instruction is correct Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example If byte EDE contains a smaller signed operand than byte TONI continue at Label1 The address EDE is within PC 32 K CMP B TONI EDE Is EDE TONI JL Label1 Yes No TONI EDE Example If the signed content of R6 is less than the memory pointed to by R7 20 bit...

Page 161: ...COFF CPUOFF and GIE are not affected Example The byte STATUS is set to 10 Then a jump to label MAINLOOP is made Data in lower 64 K program in full memory range MOV B 10 STATUS Set STATUS to 10 JMP MAINLOOP Go to main loop Example The interrupt vector TAIV of Timer_A3 is read and used for the program flow Program in full memory range but interrupt handlers always starts in lower 64 K ADD TAIV PC Ad...

Page 162: ...OFF and GIE are not affected Example The byte COUNT is tested If it is negative program execution continues at Label0 Data in lower 64 K program in full memory range TST B COUNT Is byte COUNT negative JN Label0 Yes proceed at Label0 COUNT 0 Example R6 is subtracted from R5 If the result is negative program continues at Label2 Program in full memory range SUB R6 R5 R5 R6 R5 JN Label2 R5 is negative...

Page 163: ...e jump is executed JNC is used for the test of the carry bit C JLO is used for the comparison of unsigned numbers Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example If byte EDE 15 the program continues at Label2 Unsigned data Data in lower 64 K program in full memory range CMP B 15 EDE Is EDE 15 Info to C JLO Label2 Yes EDE 15 C 0 No EDE 15 Continue E...

Page 164: ...its Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The byte STATUS is tested If it is not zero the program continues at Label3 The address of STATUS is within PC 32 K TST B STATUS Is STATUS 0 JNZ Label3 No proceed at Label3 Yes continue here Example If word EDE 1500 the program continues at Label2 Data in lower 64 K program in full memory range CMP 1500 EDE I...

Page 165: ...esses are copied to table TOM The length of the tables is 030h words Both tables reside in the lower 64 K MOV EDE R10 Prepare pointer 16 bit address Loop MOV R10 TOM EDE 2 R10 R10 points to both tables R10 2 CMP EDE 60h R10 End of table reached JLO Loop Not yet Copy completed Example The contents of table EDE byte data 16 bit addresses are copied to table TOM The length of the tables is 020h bytes...

Page 166: ...ption No operation is performed The instruction may be used for the elimination of instructions during the software check or for defined waiting times Status Bits Status bits are not affected 166 CPUX SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 167: ...EO is restored from the stack POP B LEO The low byte of the stack is moved to LEO Example The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h Example The contents of the memory pointed to by R7 and the SR are restored from the stack POP B 0 R7 The low byte of the stack is moved to the the byte which is pointed to by R7 Example ...

Page 168: ...n the low byte the high byte is not affected Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Save the two 16 bit registers R9 and R10 on the stack PUSH R9 Save R9 and R10 XXXXh PUSH R10 YYYYh Example Save the two bytes EDE and TONI on the stack The addresses EDE and TONI are within PC 32 K PUSH B EDE Save EDE xxXXh PUSH B TONI Save TONI xxYYh 168 C...

Page 169: ...ubroutine call The four MSBs of the PC 19 16 are cleared Status Bits Status bits are not affected PC 19 16 Cleared Mode Bits OSCOFF CPUOFF and GIE are not affected Example Call a subroutine SUBR in the lower 64 K and return to the address in the lower 64 K after the CALL CALL SUBR Call subroutine starting at SUBR Return by RET to here SUBR PUSH R14 Save R14 16 bit data Subroutine code POP R14 Rest...

Page 170: ...nning of the interrupt service routine The program continues at the address following the last executed instruction when the interrupt was granted The SP is incremented by two afterward Status Bits N Restored from stack C Restored from stack Z Restored from stack V Restored from stack Mode Bits OSCOFF CPUOFF and GIE are restored from stack Example Interrupt handler in the lower 64 K A 20 bit retur...

Page 171: ... the operation is performed the result has changed sign Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst 0C0h reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not af...

Page 172: ...arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst 0C0h reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted left one position RLC R5 R5 x 2 C R5 Example The input P1IN 1 information is shifted into the LSB of R5 BIT B 2 P1IN Information Carry RLC R5 Carry P0in 1 LSB ...

Page 173: ...s retained and shifted into the MSB 1 The LSB 1 is shifted into the LSB The previous LSB is shifted into the carry bit C Status Bits N Set if result is negative MSB 1 reset otherwise MSB 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The signed 16 bit number in R5 is shifted arithmetically right one position RRA R5 R...

Page 174: ...41 The carry bit C is shifted into the MSB and the LSB is shifted into the carry bit C Status Bits N Set if result is negative MSB 1 reset otherwise MSB 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM word EDE is shifted right one bit position The MSB is loaded with 1 SETC Prepare carry for MSB RRC EDE EDE EDE 1 8...

Page 175: ...MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry from MSD Example The 8 bit counter pointed to by R13 is subtracted from ...

Page 176: ...mple Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h DSUB ADD 06666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987h 06666h 09FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 R6 R6 R5 1 R6 0150h 176 CPUX SLAU272C May 2011 Revised November 2013 Submit Docu...

Page 177: ...N BIS 4 SR Emulation Description The negative bit N is set Status Bits N Set Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected 177 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 178: ...N BIS 2 SR Emulation Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected 178 CPUX SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 179: ...sitive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 16 bit constant 7654h is subtracted from RAM word EDE SUB 7654h EDE Subtract 7654h from EDE Example A table word pointed to by R5 20 bit address ...

Page 180: ...vers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 16 bit constant 7654h is subtracted from R5 with the carry from the previous instruction R5 19 16 0 SUBC W 7654h R5 Subtract 7654h C from R5 Example A 48 bit number 3 words poi...

Page 181: ...cription The high and the low byte of the operand are exchanged PC 19 16 bits are cleared in register mode Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Exchange the bytes of RAM word EDE lower 64 K MOV 1234h EDE 1234h EDE SWPB EDE 3412h EDE Figure 4 42 Swap Bytes in Memory Figure 4 43 Swap Bytes in a Register 181 SLAU272C May 2011 Revised Novemb...

Page 182: ...reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The signed 8 bit data in EDE lower 64 K is sign extended and added to the 16 bit signed data in R7 MOV B EDE R5 EDE R5 00XXh SXT R5 Sign extend low byte to R5 19 8 ADD R5 R7 Add signed 16 bit values Example The signed 8 bit dat...

Page 183: ...t affected Example R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS R7 is positive but not zero R7NEG R7 is negative R7ZERO R7 is zero Example The low byte of R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7...

Page 184: ...ise C not Z V Set if both operands are negative before execution reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Toggle bits in word CNTR 16 bit data with information bit 1 in address word TONI Both operands are located in lower 64 K XOR TONI CNTR Toggle bits in CNTR Example A table word pointed to by R5 20 bit address is used to toggle bits in R6 R6 19 16 0 XOR R5 R6 Togg...

Page 185: ...ions require an additional word of op code called the extension word All addresses indexes and immediate numbers have 20 bit values when preceded by the extension word The MSP430X extended instructions are listed and described in the following pages 185 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 186: ...its N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 40 bit counter pointed to by R12 and R13 i...

Page 187: ...o negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Ten is added to the 20 bit pointer CNTR located in two words CNTR LSBs and CNTR 2 MSBs ADDX A 10 CNTR Add 10 to 20 bit pointer Example A table word 16 bit pointed to by R5 20 bit address is added to R6 The jump to label TONI is performed on a carry ADDX W R5 R6 Add table word to R6 JC TONI Jump ...

Page 188: ...lt of two positive operands is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Constant 15 and the carry of the previous instruction are added to the 20 bit counter CNTR located in two words ADDCX A 15 CNTR Add 15 C to 20 bit CNTR Example A table word pointed to by R5 20 bit address and the carry C are added to ...

Page 189: ...ve MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits set in R5 20 bit data are used as a mask AAA55h for the address word TOM located in two words If the result is zero a branch is taken to label TONI MOVA AAA55h R5 Load 20 bit mask to R5 ANDX A R5 TOM TOM and R5 TOM JZ TON...

Page 190: ...rce operand is not affected Both operands may be located in the full address space Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits 19 15 of R5 20 bit data are cleared BICX A 0F8000h R5 Clear R5 19 15 bits Example A table word pointed to by R5 20 bit address is used to clear bits in R7 R7 19 16 0 BICX W R5 R7 ...

Page 191: ...e operand is not affected Both operands may be located in the full address space Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Bits 16 and 15 of R5 20 bit data are set to one BISX A 018000h R5 Set R5 16 15 bits Example A table word pointed to by R5 20 bit address is used to set bits in R7 BISX W R5 R7 Set bits in R7...

Page 192: ...o reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example Test if bit 16 or 15 of R5 20 bit data is set Jump to label TONI if so BITX A 018000h R5 Test R5 16 15 bits JNZ TONI At least one bit is set Both are reset Example A table word pointed to by R5 20 bit address is used to test bits in R7 Jump to label TONI if at least one bit is set BITX W R5 R7 Test bits in R...

Page 193: ... B dst Operation 0 dst MOVX A 0 dst Emulation MOVX 0 dst MOVX B 0 dst Description The destination operand is cleared Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM address word TONI is cleared CLRX A TONI 0 TONI 193 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 194: ... or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example Compare EDE with a 20 bit constant 18000h Jump to label TONI if EDE equals the constant CMPX A 018000h EDE Compare EDE with 18000h JEQ TONI EDE contains 18000h Not equal Example A table word pointed t...

Page 195: ...he destination Status Bits N Set if MSB of result is 1 address word 79999h word 7999h byte 79h reset if MSB is 0 Z Set if result is zero reset otherwise C Set if the BCD result is too large address word 99999h word 9999h byte 99h reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 40 bit counter pointed to by R12 and R13 is incremented decimally DADDX A 1 0 R12...

Page 196: ...1 address word 79999h word 7999h byte 79h reset if MSB is 0 Z Set if result is zero reset otherwise C Set if the BCD result is too large address word 99999h word 9999h byte 99h reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example Decimal 10 is added to the 20 bit BCD counter DECCNTR located in two words DADDX A 10h DECCNTR Add 10 to 20 bit BCD counter Example The ei...

Page 197: ...perand is decremented by one The original contents are lost Status Bits N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM address word TONI is decremented by one DECX A TONI Decrement TONI 197 SLAU272C May ...

Page 198: ...estination operand is decremented by two The original contents are lost Status Bits N Set if result is negative reset if positive Z Set if dst contained 2 reset otherwise C Reset if dst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM address word TONI is decremented by two DECDX A TONI Decrement TONI...

Page 199: ...tained 0FFFFFh reset otherwise Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise C Set if dst contained 0FFFFFh reset otherwise Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07FFFh reset otherwise Set if dst contained 07Fh reset otherwise Mode Bits OSCOFF C...

Page 200: ...herwise Set if dst contained 0FFFEh reset otherwise Set if dst contained 0FEh reset otherwise C Set if dst contained 0FFFFEh or 0FFFFFh reset otherwise Set if dst contained 0FFFEh or 0FFFFh reset otherwise Set if dst contained 0FEh or 0FFh reset otherwise V Set if dst contained 07FFFEh or 07FFFFh reset otherwise Set if dst contained 07FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07F...

Page 201: ...Fh reset otherwise Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example 20 bit content of R5 is negated 2s complement INVX A R5 Invert R5 INCX A R5 R5 is now negated Example Content of memory...

Page 202: ...Loop MOVX W R10 TOM EDE 2 R10 R10 points to both tables R10 2 CMPA EDE 60h R10 End of table reached JLO Loop Not yet Copy completed Example The contents of table EDE byte data 20 bit addresses are copied to table TOM The length of the table is 020h bytes MOVA EDE R10 Prepare pointer 20 bit MOV 20h R9 Prepare counter Loop MOVX W R10 TOM EDE 2 R10 R10 points to both tables R10 1 DEC R9 Decrement cou...

Page 203: ...ng MOVX A z20 Rsrc Rdst MOVA z16 Rsrc Rdst Indexed Reg MOVX A Rsrc z20 Rdst MOVA Rsrc z16 Rdst Reg Indexed MOVX A symb20 Rdst MOVA symb16 Rdst Symbolic Reg MOVX A Rsrc symb20 MOVA Rsrc symb16 Reg Symbolic 203 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 204: ...oes not use the extension word Description POPM A The CPU registers pushed on the stack are moved to the extended CPU registers starting with the CPU register Rdst n 1 The SP is incremented by n 4 after the operation POPM W The 16 bit registers pushed on the stack are moved back to the CPU registers starting with CPU register Rdst n 1 The SP is incremented by n 2 after the instruction The MSBs Rds...

Page 205: ...ored on the stack The SP is decremented by n 4 after the operation The data Rn 19 0 of the pushed CPU registers is not affected PUSHM W The n registers starting with Rdst backwards are stored on the stack The SP is decremented by n 2 after the operation The data Rn 19 0 of the pushed CPU registers is not affected Note This instruction does not use the extension word Status Bits Status bits are not...

Page 206: ... Emulation Description The item on TOS is written to the destination operand Register mode Indexed mode Symbolic mode and Absolute mode are possible The SP is incremented by two or four Note the SP is incremented by two also for byte operations Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Write the 16 bit value on TOS to the 20 bit address EDE P...

Page 207: ...he write operation Description The SP is decremented by two byte and word operands or by four address word operand Then the source operand is written to the TOS All seven addressing modes are possible for the source operand Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Save the byte at the 20 bit address EDE on the stack PUSHX B EDE Save byte at ...

Page 208: ...4 8 or 16 The word instruction RLAM W clears the bits Rdst 19 16 Note This instruction does not use the extension word Status Bits N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the MSB n 1 MSB 1 n 2 MSB 2 n 3 MSB 3 n 4 V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 20 bit ope...

Page 209: ...multiplication by 2 Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 040000h dst 0C0000h reset otherwise Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst 0C0h ...

Page 210: ...Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 040000h dst 0C0000h reset otherwise Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst 0C0h reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 20 ...

Page 211: ...nstruction RRAM W clears the bits Rdst 19 16 Note This instruction does not use the extension word Status Bits N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The signed 20 bit number in R5 is s...

Page 212: ... division by 2 All other modes for the destination the destination operand is shifted right arithmetically by one bit position as shown in Figure 4 49 The MSB retains its value sign the LSB is shifted into the carry bit RRAX here operates equal to a signed division by 2 All addressing modes with the exception of the Immediate mode are possible in the full memory Status Bits N Set if result is nega...

Page 213: ...www ti com Instruction Set Description RRAX B EDE EDE 2 EDE Figure 4 48 Rotate Right Arithmetically RRAX B A Register Mode Figure 4 49 Rotate Right Arithmetically RRAX B A Non Register Mode 213 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 214: ...Figure 4 50 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit The word instruction RRCM W clears the bits Rdst 19 16 Note This instruction does not use the extension word Status Bits N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 ...

Page 215: ... MSB 2 RRCM A 3 R5 R5 R5 3 20000h Example The word in R6 is shifted right by two positions The MSB is loaded with the LSB The MSB 1 is loaded with the contents of the carry flag RRCM W 2 R6 R6 R6 2 R6 19 16 0 Figure 4 50 Rotate Right Through Carry RRCM W and RRCM A 215 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 216: ...er modes for the destination the destination operand is shifted right by one bit position as shown in Figure 4 52 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit All addressing modes with the exception of the Immediate mode are possible in the full memory Status Bits N Set if result is negative A dst 19 1 reset if dst 19 0 W dst 15 1 reset if dst 15 0 B dst 7 1 reset ...

Page 217: ...i com Instruction Set Description RPT 12 RRCX W R6 R6 R6 12 R6 19 16 0 Figure 4 51 Rotate Right Through Carry RRCX B A Register Mode Figure 4 52 Rotate Right Through Carry RRCX B A Non Register Mode 217 SLAU272C May 2011 Revised November 2013 CPUX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 218: ... 8 or 16 The word instruction RRUM W clears the bits Rdst 19 16 Note This instruction does not use the extension word Status Bits N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The unsigned add...

Page 219: ...in Figure 4 54 The word instruction RRUX W clears the bits Rdst 19 16 The byte instruction RRUX B clears the bits Rdst 19 8 Zero is shifted into the MSB the LSB is shifted into the carry bit Status Bits N Set if result is negative A dst 19 1 reset if dst 19 0 W dst 15 1 reset if dst 15 0 B dst 7 1 reset if dst 7 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCO...

Page 220: ...e lost Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter poin...

Page 221: ...from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 20 bit constant 87654h is subtracted from EDE LSBs and EDE 2 MSBs SUBX A 87654h EDE Subtract 87654h from EDE 2 EDE Example A table word ...

Page 222: ... if the subtraction of a negative source operand from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 20 bit constant 87654h is subtracted from R5 with the carry from the previous instructi...

Page 223: ...16 are cleared Other modes When the A extension is used bits 31 20 of the destination address are cleared bits 19 16 are left unchanged and bits 15 8 are swapped with bits 7 0 When the W extension is used bits 15 8 are swapped with bits 7 0 of the addressed word Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Exchange the bytes of RAM address word ...

Page 224: ...e High Byte High Byte Before SWPBX After SWPBX X 0 19 19 16 16 Instruction Set Description www ti com Figure 4 57 Swap Bytes SWPBX W Register Mode Figure 4 58 Swap Bytes SWPBX W In Memory 224 CPUX SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 225: ... the low byte of the operand dst 7 is extended into dst 19 8 The bits dst 31 20 are cleared SXTX W the sign of the low byte of the operand dst 7 is extended into dst 15 8 Status Bits N Set if result is negative reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The signed 8 bit...

Page 226: ...is not affected Status Bits N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM byte LEO is tested PC is pointing to upper memory If it is negative continue at LEONEG if it is positive but not zero continue at LEOPOS TSTX B LEO Test LEO JN LEONEG LEO is negative JZ LEOZERO L...

Page 227: ...f positive MSB 0 Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise carry not Zero V Set if both operands are negative before execution reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Toggle bits in address word CNTR 20 bit data with information in address word TONI 20 bit address XORX A TONI CNTR Toggle bits in CNTR Example A table word po...

Page 228: ... the Register mode and the Immediate mode except for the MOVA instruction Restricting the addressing modes removes the need for the additional extension word op code improving code density and execution time The MSP430X address instructions are listed and described in the following pages 228 CPUX SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instru...

Page 229: ...t if positive Rdst 19 0 Z Set if result is zero reset otherwise C Set if there is a carry from the 20 bit result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is increased by 0A4320h The jump to TONI is performed if a carry occurs ADDA 0A4320h ...

Page 230: ... to address BRA EDE MOVA imm20 PC BRA 01AA04h Symbolic mode Branch to the 20 bit address contained in addresses EXEC LSBs and EXEC 2 MSBs EXEC is located at the address PC X where X is within 32 K Indirect addressing BRA EXEC MOVA z16 PC PC Note If the 16 bit index is not sufficient a 20 bit index may be used with the following instruction MOVX A EXEC PC 1M byte range with 20 bit index Absolute mo...

Page 231: ...5 MOVA R5 PC R5 4 Indexed mode Branch to the 20 bit address contained in the address pointed to by register R5 X for example a table with addresses starting at X R5 X points to the LSBs R5 X 2 points to the MSBs of the address X is within R5 32 K Indirect indirect R5 X BRA X R5 MOVA z16 R5 PC Note If the 16 bit index is not sufficient a 20 bit index X may be used with the following instruction MOV...

Page 232: ... Examples Examples for all addressing modes are given Immediate mode Call a subroutine at label EXEC or call directly an address CALLA EXEC Start address EXEC CALLA 01AA04h Start address 01AA04h Symbolic mode Call a subroutine at the 20 bit address contained in addresses EXEC LSBs and EXEC 2 MSBs EXEC is located at the address PC X where X is within 32 K Indirect addressing CALLA EXEC Start addres...

Page 233: ... address in the table pointed to by R5 Indirect indirect R5 CALLA R5 Start address at R5 R5 4 Indexed mode Call a subroutine at the 20 bit address contained in the address pointed to by register R5 X for example a table with addresses starting at X R5 X points to the LSBs R5 X 2 points to the MSBs of the word address X is within R5 32 K Indirect indirect R5 X CALLA X R5 Start address at R5 X z16 R...

Page 234: ...ration 0 Rdst MOVA 0 Rdst Emulation Description The destination register is cleared Status Bits Status bits are not affected Example The 20 bit value in R10 is cleared CLRA R10 0 R10 234 CPUX SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 235: ...Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 20 bit immediate operand and R6 are compared If they are equal the program continues...

Page 236: ...tatus Bits N Set if result is negative reset if positive Z Set if Rdst contained 2 reset otherwise C Reset if Rdst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 20 bit value in R5 is decremented by 2 DECDA R5 Decrement R5 by two 236 CPUX SLAU272C May 2011 Revised November 2013 Submit Documentation ...

Page 237: ...contained 0FEh reset otherwise C Set if Rdst contained 0FFFFEh or 0FFFFFh reset otherwise Set if Rdst contained 0FFFEh or 0FFFFh reset otherwise Set if Rdst contained 0FEh or 0FFh reset otherwise V Set if Rdst contained 07FFFEh or 07FFFFh reset otherwise Set if Rdst contained 07FFEh or 07FFFh reset otherwise Set if Rdst contained 07Eh or 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not...

Page 238: ...py 20 bit value in R9 to R8 MOVA R9 R8 R9 R8 Write 20 bit immediate value 12345h to R12 MOVA 12345h R12 12345h R12 Copy 20 bit value addressed by R9 100h to R8 Source operand in addresses R9 100h LSBs and R9 102h MSBs MOVA 100h R9 R8 Index 32 K 2 words transferred Move 20 bit value in 20 bit absolute addresses EDE LSBs and EDE 2 MSBs to R12 MOVA EDE R12 EDE R12 2 words transferred Move 20 bit valu...

Page 239: ...Destination operand in addresses R9 100h LSBs and R9 102h MSBs MOVA R8 100h R9 Index 32 K 2 words transferred Move 20 bit value in R13 to 20 bit absolute addresses EDE LSBs and EDE 2 MSBs MOVA R13 EDE R13 EDE 2 words transferred Move 20 bit value in R13 to 20 bit addresses EDE LSBs and EDE 2 MSBs PC index 32 K MOVA R13 EDE R13 EDE 2 words transferred 239 SLAU272C May 2011 Revised November 2013 CPU...

Page 240: ...t affected This allows the transfer of information with these bits Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Call a subroutine SUBR from anywhere in the 20 bit address space and return to the address after the CALLA CALLA SUBR Call subroutine starting at SUBR Return by RETA to here SUBR PUSHM A 2 R14 Save R14 an...

Page 241: ... Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB Rdst 19 reset otherwise V Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUO...

Page 242: ...tion register is negative reset if positive Z Set if destination register contains zero reset otherwise C Set V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 20 bit value in R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TSTA R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS R7 is positive but not zero R7NEG R7 is ...

Page 243: ...c Page 5 1 FRAM Introduction 244 5 2 FRAM Organization 244 5 3 FRCTL Module Operation 244 5 4 Programming FRAM Memory Devices 245 5 5 Wait State Control 245 5 6 FRAM ECC 246 5 7 FRCTL Registers 247 243 SLAU272C May 2011 Revised November 2013 FRAM Controller FRCTL Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 244: ...he same fashion as SRAM All writes to user protected segments are handled as described in the Memory Protection Unit chapter An FRAM read always requires a write back to the same memory location with the same information read This write back is part of the FRAM module itself and requires no user interaction These write backs are different from the normal write access from application code The FRAM...

Page 245: ...le time requirements For these scenarios a wait state generator mechanism is implemented There are two modes to control the wait state generation automatic and manual When required the system clock CPU or DMA is held until the FRAM access and cycle time constraints are met 5 5 1 Manual Wait State Control The complete FRAM cycle time is defined by two timings access time and precharge time which ca...

Page 246: ...system speed However if none of the words available in the cache are requested a cache miss the wait state controls the CPU to ensure proper FRAM access 5 5 4 Safe Access The Safe Access is implemented to ensure correct FRAM access in Manual Wait State Mode Safe Access is active when the user configures the NACCESS 2 0 and NPRECHG 2 0 bits to values that do not meet the required FRAM timing for th...

Page 247: ... have word or byte register access For a generic register ANYREG the suffix _L ANYREG_L refers to the lower byte of the register bits 0 through 7 The suffix _H ANYREG_H refers to the upper byte of the register bits 8 through 15 Table 5 2 FRCTL Registers Offset Acronym Register Name Type Access Reset Section 00h FRCTL0 FRAM Controller Control 0 Read write Word 9608h Section 5 7 1 00h FRCTL0_L Read ...

Page 248: ... disables the access and no PUC is generated 7 Reserved R 0h Reserved Always reads as 0 6 4 NACCESS RW 0h Wait state generator access time control Each wait state adds a N integer multiple increase of the IFCLK period where N 0 through 7 N 0 implies no wait states 3 NAUTO RW 0h Disables the wait state generator and manual settings rather controls wait state with internal FRAM state machine 0b Manu...

Page 249: ...Generates vector in SYSRSTIV 6 UBDIEN RW 0h Enable NMI event if uncorrectable bit error detected The bits UBDRSTEN and UBDIEN are mutually exclusive and are not allowed to be set simultaneously Only one error handling can be selected at one time 0b Uncorrectable bit detection interrupt disabled 1b Uncorrectable bit detection interrupt enabled Generates vector in SYSSNIV 5 CBDIEN RW 0h Enable NMI e...

Page 250: ...bit error flag This interrupt flag is set if an uncorrectable bit error has been detected in the FRAM memory error detection logic This bit is cleared by software or by reading the system NMI vector word SYSSNIV if it is the highest pending interrupt flag This bit is write 0 only and write 1 has no effect 0b No interrupt pending 1b Interrupt pending Can be cleared by user or by reading SYSSNIV 1 C...

Page 251: ...rotection Unit Topic Page 6 1 Memory Protection Unit MPU Introduction 252 6 2 MPU Segments 253 6 3 MPU Access Management Settings 255 6 4 MPU Violations 256 6 5 MPU Registers 257 251 SLAU272C May 2011 Revised November 2013 Memory Protection Unit MPU Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 252: ...ictions for read write and execute operations MPU features include Main memory can be configured up to three segments of variable size Access rights for each segment can be set independently Information memory can have its access rights set independently All MPU registers are protected from access by password NOTE After BOR no segmentation exists and the main memory and information memory are acce...

Page 253: ...stly the end of segment 3 is given by the highest main memory address as defined in the device specific data sheet The segmentation of the main memory is shown in Figure 6 2 The address bus MAB is analyzed by the MPU along with the current border settings to determine which segment of memory is selected If the address is lower than B1 and B2 segment 1 is selected For address values between B1 and ...

Page 254: ...F17Fh 3 03h C600h C7FFh E300h E3FFh F180h F1FFh 4 04h C800h C9FFh E400h E4FFh F200h F27Fh 5 05h CA00h CBFFh E500h E5FFh F280h F2FFh 6 06h CC00h CDFFh E600h E6FFh F300h F37Fh 7 07h CE00h CFFFh E700h E7FFh F380h F3FFh 8 08h D000h D1FFh E800h E8FFh F400h F47Fh 9 09h D200h D3FFh E900h E9FFh F480h F4FFh 10 0Ah D400h D5FFh EA00h EAFFh F500h F57Fh 11 0Bh D600h D7FFh EB00h EBFFh F580h F5FFh 12 0Ch D800h D...

Page 255: ... and is also addressable from 01900h to 019FFh 6 3 MPU Access Management Settings Each segment described in Section 6 2 2 and Section 6 2 3 can have read write and execute access rights set independently The MPUSAM register allows setting the access rights for the four segments information memory segment three main memory segments MPUSEGxRE enables read access for segment x MPUSEGxWE enables write...

Page 256: ...ts If an interrupt or a reset occurs and this segment is read protected the MPU automatically allows access to the interrupt vector memory space In this scenario only the interrupt vector table is accessible Access to the interrupt routine itself is not automatically enabled NOTE Only the interrupt table and the reset vector are opened on an interrupt or reset occurrence If the application protect...

Page 257: ... refers to the upper byte of the register bits 8 through 15 Table 6 3 MPU Registers Offset Acronym Register Name Type Access Reset Section 00h MPUCTL0 Memory Protection Unit Control 0 Read write Word 9600h Section 6 5 1 00h MPUCTL0_L Read Write Byte 00h 01h MPUCTL0_H Read Write Byte 96h 02h MPUCTL1 Memory Protection Unit Control 1 Read write Word 0000h Section 6 5 2 02h MPUCTL1_L Read Write Byte 0...

Page 258: ...a correct password is written all MPU registers are accessible An incorrect password written in byte mode disables MPU register access and no PUC is generated 7 5 Reserved R 0h Reserved Always reads as 0 4 Reserved RW 0h Reserved Must always be written as 0 3 2 Reserved R 0h Reserved Always reads as 0 1 Reserved RW 0h Reserved Must always be written as 0 0 MPUENA MPU enable This bit enables the MP...

Page 259: ...t 3 is detected This bit is cleared by software or by reading the reset vector word SYSRSTIV if it is the highest pending interrupt flag This bit is write 0 only Write 1 has no effect 0b No interrupt pending 1b Interrupt pending 1 MPUSEG2IFG RW 0h Main memory segment 2 violation interrupt flag This bit is set if an access violation in main memory segment 2 is detected This bit is cleared by softwa...

Page 260: ...t Field Type Reset Description 15 13 Reserved R 0h Reserved Always reads as 0 12 8 MPUSB2 RW 0h MPU segment border 2 After BOR these bits are automatically set to 0 and only segment 3 is active 7 5 Reserved R 0h Reserved Always reads as 0 4 0 MPUSB1 RW 0h MPU segment border 1 After BOR these bits are automatically set to 0 and only segment 3 is active 260 Memory Protection Unit MPU SLAU272C May 20...

Page 261: ...ess of user information memory 0b Reads of user information memory causes a violation if MPUSEGIWE MPUSEGIXE 0 1b Reads of user information memory is allowed 11 MPUSEG3VS RW 0h MPU main memory segment 3 violation select If set a PUC must be executed on illegal access to main memory segment 3 0b Violation in main memory segment 3 asserts the MPUSEG3IFG bit 1b Violation in main memory segment 3 asse...

Page 262: ...et a PUC must be executed on illegal access to main memory segment 1 0b Violation in main memory segment 1 asserts the MPUSEG1IFG bit 1b Violation in main memory segment 1 asserts the MPUSEG1IFG bit and a PUC is executed 2 MPUSEG1XE RW 1h MPU main memory segment 1 execute enable If set this bit enables execution in main memory segment 1 0b Execution in main memory segment 1 causes a violation 1b E...

Page 263: ...emory protection interrupt vector value 00h No interrupt pending 02h Interrupt Source SEGI Violation Interrupt Flag SEGIIFG Interrupt Priority Highest 04h Interrupt Source SEG1 Violation Interrupt Flag SEG1IFG 06h Interrupt Source SEG2 Violation Interrupt Flag SEG2IFG 08h Interrupt Source SEG3 Violation Interrupt Flag SEG3IFG Interrupt Priority Lowest 263 SLAU272C May 2011 Revised November 2013 Me...

Page 264: ...ress to another without CPU intervention This chapter describes the operation of the DMA controller Topic Page 7 1 Direct Memory Access DMA Introduction 265 7 2 DMA Operation 267 7 3 DMA Registers 279 264 DMA Controller SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 265: ...roller can increase the throughput of peripheral modules It can also reduce system power consumption by allowing the CPU to remain in a low power mode without having to awaken to move data to or from a peripheral DMA controller features include Up to eight independent transfer channels Configurable DMA channel priorities Requires only two MCLK clock cycles per transfer Byte word or mixed byte and ...

Page 266: ...pace NMI Interrupt Request JTAG Active Halt Halt CPU ROUNDROBIN DMARMWDIS DMAnTSEL DMA0TRIG31 DMA0TRIG0 DMA0TSEL 5 DMA0TRIG1 00000 00001 11111 DMA1TRIG31 DMA1TRIG0 DMA1TSEL 5 DMA1TRIG1 00000 00001 11111 DMAnTRIG31 DMAnTRIG0 5 DMAnTRIG1 00000 00001 11111 DMA Priority and Control Direct Memory Access DMA Introduction www ti com Figure 7 1 DMA Controller Block Diagram 266 DMA Controller SLAU272C May ...

Page 267: ...wn in Figure 7 2 The addressing modes are Fixed address to fixed address Fixed address to block of addresses Block of addresses to fixed address Block of addresses to block of addresses The addressing modes are configured with the DMASRCINCR and DMADSTINCR control bits The DMASRCINCR bits select if the source address is incremented decremented or unchanged after each transfer The DMADSTINCR bits s...

Page 268: ...rd or any combination Table 7 1 DMA Transfer Modes DMADT Transfer Mode Description 000 Single transfer Each transfer requires a trigger DMAEN is automatically cleared when DMAxSZ transfers have been made 001 Block transfer A complete block is transferred with one trigger DMAEN is automatically cleared at the end of the block transfer 010 011 Burst block transfer CPU activity is interleaved with a ...

Page 269: ...and DMASRCINCR bits select if the destination address and the source address are incremented or decremented after each transfer If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer The DMAxSZ register is decremented after each transfer When the DMAxSZ re...

Page 270: ...emporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set During a block transfe...

Page 271: ... DMAxSZ 0 OR DMAEN 0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAREQ 0 T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMADT 5 AND DMAxSZ 0 AND DMAEN 1 DMAEN 0 DMAEN 1 DMAEN 0 DMAREQ 0 T_Size DMAxSZ DMAABORT 1 2 MCLK DMAEN 0 www ti com DMA Operation Figure 7 4 DMA Block Transfer State Diagram 271 SLAU272C May 2011 Revised November 2013 DMA Controller Submit Documentation Feedback Copyri...

Page 272: ... DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG...

Page 273: ...MALEVEL 1 AND Trigger 0 DMADT 2 3 AND DMAxSZ 0 OR DMAEN 0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAxSZ DMAEN 0 DMAEN 1 DMAxSZ 0 DMAxSZ 0 AND a multiple of 4 words bytes were transferred DMAxSZ 0 DMAEN 0 DMAREQ 0 T_Size DMAxSZ www ti com DMA Operation Figure 7 5 DMA Burst Block Transfer State Diagram 273 SLAU272C May 2011 Revised November 2013 ...

Page 274: ...rst block transfer 7 2 3 2 Level Sensitive Triggers When DMALEVEL 1 level sensitive triggers are used For proper operation level sensitive triggers can only be used when external trigger DMAE0 is selected as the trigger DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set The trigger signal must remain high for a block or burst block transfer to complete ...

Page 275: ...triggered when eUSCI_Ax is ready to transmit new data UCAxTXIFG is automatically reset when the transfer starts If UCAxTXIE is set the UCAxTXIFG does not trigger a transfer eUSCI_Bx A transfer is triggered when eUSCI_Bx receives new data UCBxRXIFG is automatically reset when the transfer starts If UCBxRXIE is set the UCBxRXIFG does not trigger a transfer A transfer is triggered when eUSCI_Bx is re...

Page 276: ...Mx parameter in the data sheet 7 2 8 Using DMA With System Interrupts DMA transfers are not interruptible by system interrupts System interrupts remain pending until the completion of the transfer NMIs can interrupt the DMA controller if the ENNMI bit is set System interrupt service routines are interrupted by DMA transfers If an interrupt service routine or other routine must execute with no inte...

Page 277: ...ctor 14 DMA channel 6 2 JMP DMA7_HND Vector 16 DMA channel 7 2 DMA7_HND Vector 16 DMA channel 7 Task starts here RETI Back to main program 5 DMA6_HND Vector 14 DMA channel 6 Task starts here RETI Back to main program 5 DMA5_HND Vector 12 DMA channel 5 Task starts here RETI Back to main program 5 DMA4_HND Vector 10 DMA channel 4 Task starts here RETI Back to main program 5 DMA3_HND Vector 8 DMA cha...

Page 278: ...hroughput of the ADC10 module and enhances low power applications allowing the CPU to remain off while data transfers occur A transfer is triggered when the conversion is completed and the ADC10IFG0 is set Setting the ADC10IFG0 with software does not trigger a transfer The ADC10IFG0 flag is automatically reset when the ADC10MEM0 register is accessed by the DMA controller 278 DMA Controller SLAU272...

Page 279: ...Word undefined Section 7 3 7 double word 06h DMA2DA DMA Channel 2 Destination Address Read write Word undefined Section 7 3 8 double word 0Ah DMA2SZ DMA Channel 2 Transfer Size Read write Word undefined Section 7 3 9 00h DMA3CTL DMA Channel 3 Control Read write Word 0000h Section 7 3 6 02h DMA3SA DMA Channel 3 Source Address Read write Word undefined Section 7 3 7 double word 06h DMA3DA DMA Channe...

Page 280: ...DMA Channel 7 Source Address Read write Word undefined Section 7 3 7 double word 06h DMA7DA DMA Channel 7 Destination Address Read write Word undefined Section 7 3 8 double word 0Ah DMA7SZ DMA Channel 7 Transfer Size Read write Word undefined Section 7 3 9 280 DMA Controller SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 281: ...DMA transfer trigger See the device specific data sheet for number of channels and trigger assignment 00000b DMA1TRIG0 00001b DMA1TRIG1 00010b DMA1TRIG2 11110b DMA1TRIG30 11111b DMA1TRIG31 7 5 Reserved R 0h Reserved Always reads as 0 4 0 DMA0TSEL RW 0h DMA trigger select These bits select the DMA transfer trigger See the device specific data sheet for number of channels and trigger assignment 0000...

Page 282: ...DMA transfer trigger See the device specific data sheet for number of channels and trigger assignment 00000b DMA3TRIG0 00001b DMA3TRIG1 00010b DMA3TRIG2 11110b DMA3TRIG30 11111b DMA3TRIG31 7 5 Reserved R 0h Reserved Always reads as 0 4 0 DMA2TSEL RW 0h DMA trigger select These bits select the DMA transfer trigger See the device specific data sheet for number of channels and trigger assignment 0000...

Page 283: ...DMA transfer trigger See the device specific data sheet for number of channels and trigger assignment 00000b DMA5TRIG0 00001b DMA5TRIG1 00010b DMA5TRIG2 11110b DMA5TRIG30 11111b DMA5TRIG31 7 5 Reserved R 0h Reserved Always reads as 0 4 0 DMA4TSEL RW 0h DMA trigger select These bits select the DMA transfer trigger See the device specific data sheet for number of channels and trigger assignment 0000...

Page 284: ...DMA transfer trigger See the device specific data sheet for number of channels and trigger assignment 00000b DMA7TRIG0 00001b DMA7TRIG1 00010b DMA7TRIG2 11110b DMA7TRIG30 11111b DMA7TRIG31 7 5 Reserved R 0h Reserved Always reads as 0 4 0 DMA6TSEL RW 0h DMA trigger select These bits select the DMA transfer trigger See the device specific data sheet for number of channels and trigger assignment 0000...

Page 285: ...ur during read modify write CPU operations 1b DMA transfers inhibited during read modify write CPU operations 1 ROUNDROBIN RW 0h Round robin This bit enables the round robin DMA channel priorities 0b DMA channel priority is DMA0 DMA1 DMA2 DMA7 1b DMA channel priority changes with each transfer 0 ENNMI RW 0h Enable NMI This bit enables the interruption of a DMA transfer by an NMI When an NMI interr...

Page 286: ...remented DMAxDA is not incremented or decremented 00b Destination address is unchanged 01b Destination address is unchanged 10b Destination address is decremented 11b Destination address is incremented 9 8 DMASRCINCR RW 0h DMA source increment This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer When DMASRCBYTE 1 the source address increments...

Page 287: ...sabled 1b Enabled 1 DMAABORT RW 0h DMA abort This bit indicates if a DMA transfer was interrupt by an NMI 0b DMA transfer not interrupted 1b DMA transfer interrupted by NMI 0 DMAREQ RW 0h DMA request Software controlled DMA start DMAREQ is reset automatically 0b No DMA start 1b Start DMA 287 SLAU272C May 2011 Revised November 2013 DMA Controller Submit Documentation Feedback Copyright 2011 2013 Te...

Page 288: ...s as 0 19 0 DMAxSA RW undefined DMA source address The source address register points to the DMA source address for single transfers or the first source address for block transfers The source address register remains unchanged during block and burst block transfers There are two words for the DMAxSA register Bits 31 20 are reserved and always read as zero Reading or writing bits 19 16 requires the...

Page 289: ...0 DMAxDA RW undefined DMA destination address The destination address register points to the DMA destination address for single transfers or the first destination address for block transfers The destination address register remains unchanged during block and burst block transfers There are two words for the DMAxDA register Bits 31 20 are reserved and always read as zero Reading or writing bits 19 ...

Page 290: ...gister defines the number of byte or word data per block transfer DMAxSZ register decrements with each word or byte transfer When DMAxSZ decrements to 0 it is immediately and automatically reloaded with its previously initialized value 0000h Transfer is disabled 0001h One byte or word is transferred 0002h Two bytes or words are transferred FFFFh 65535 bytes or words are transferred 290 DMA Control...

Page 291: ...IFG Interrupt Priority Highest 04h Interrupt Source DMA channel 1 Interrupt Flag DMA1IFG 06h Interrupt Source DMA channel 2 Interrupt Flag DMA2IFG 08h Interrupt Source DMA channel 3 Interrupt Flag DMA3IFG 0Ah Interrupt Source DMA channel 4 Interrupt Flag DMA4IFG 0Ch Interrupt Source DMA channel 5 Interrupt Flag DMA5IFG 0Eh Interrupt Source DMA channel 6 Interrupt Flag DMA6IFG 10h Interrupt Source ...

Page 292: ...the digital I O ports in all devices Topic Page 8 1 Digital I O Introduction 293 8 2 Digital I O Operation 294 8 3 I O Configuration 297 8 4 Digital I O Registers 300 292 Digital I O SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 293: ...d accessed by word formats Port pairs P1 and P2 P3 and P4 P5 and P6 P7 and P8 and so on are associated with the names PA PB PC PD and so on respectively All port registers are handled in this manner with this naming convention except for the interrupt vector registers P1IV and P2IV that is PAIV does not exist When writing to port PA with word operations all 16 bits are written to the port When wri...

Page 294: ...s pullup or pulldown Bit 0 Pin is pulled down Bit 1 Pin is pulled up 8 2 3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the corresponding I O pin regardless of the selected function for the pin PxDIR bits for I O pins that are selected for other functions must be set as required by the other function Bit 0 Port pin is switched to input direction Bit 1 Port pin...

Page 295: ... to write both P1SEL1 01h and P1SEL0 01h This is not possible without first passing through an intermediate configuration and this configuration may not be desirable from an application standpoint The PxSELC complement register can be used to handle such situations The PxSELC register always reads 0 Each set bit of the PxSELC register complements the corresponding respective bit of the PxSEL1 and ...

Page 296: ... jump to the appropriate routine The code to handle any other PxIV register is similar The numbers at the right margin show the number of CPU cycles that are required for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself Interrupt handler for P1 Cycles P1_HND Interrupt latency 6 ADD P1...

Page 297: ...cluding unused ones Section 8 3 2 should be configured according to the application needs as early as possible during the initialization procedure 8 3 2 Configuration of Unused Port Pins To prevent a floating input and to reduce power consumption unused I O pins should be configured as I O function output direction and left unconnected on the PC board The value of the PxOUT bit is don t care becau...

Page 298: ...a sheet for availability To wake up the device a port pin must be configured properly prior to entering LPMx 5 Each port should be configured as general purpose input Pulldowns or pullups can be applied if required Setting the PxIES bit of the corresponding register determines the edge transition that wakes the device Last the PxIE for the port must be enabled as well as the general interrupt enab...

Page 299: ...s occurred on various ports In these cases multiple PxIFG flags are set and it cannot be determined which port caused the I O wakeup 299 SLAU272C May 2011 Revised November 2013 Digital I O Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 300: ...tion 8 4 3 2Eh P3IV_L Read only Byte 00h 2Fh P3IV_H Read only Byte 00h 3Eh P4IV Port 4 Interrupt Vector Read only Word 0000h Section 8 4 4 3Eh P4IV_L Read only Byte 00h 3Fh P4IV_H Read only Byte 00h 00h P1IN Port 1 Input Read only Byte undefined Section 8 4 5 or PAIN_L 02h P1OUT Port 1 Output Read write Byte undefined Section 8 4 6 or PAOUT_L 04h P1DIR Port 1 Direction Read write Byte 00h Section ...

Page 301: ...on 8 4 13 or PAIE_H 1Dh P2IFG Port 2 Interrupt Flag Read write Byte 00h Section 8 4 14 or PAIFG_H 00h P3IN Port 3 Input Read only Byte undefined Section 8 4 5 or PBIN_L 02h P3OUT Port 3 Output Read write Byte undefined Section 8 4 6 or PBOUT_L 04h P3DIR Port 3 Direction Read write Byte 00h Section 8 4 7 or PBDIR_L 06h P3REN Port 3 Resistor Enable Read write Byte 00h Section 8 4 8 or PBREN_L 0Ah P3...

Page 302: ...on 8 4 13 or PBIE_H 1Dh P4IFG Port 4 Interrupt Flag Read write Byte 00h Section 8 4 14 or PBIFG_H 00h P5IN Port 5 Input Read only Byte undefined Section 8 4 5 or PCIN_L 02h P5OUT Port 5 Output Read write Byte undefined Section 8 4 6 or PCOUT_L 04h P5DIR Port 5 Direction Read write Byte 00h Section 8 4 7 or PCDIR_L 06h P5REN Port 5 Resistor Enable Read write Byte 00h Section 8 4 8 or PCREN_L 0Ah P5...

Page 303: ...on 8 4 13 or PCIE_H 1Dh P6IFG Port 6 Interrupt Flag Read write Byte 00h Section 8 4 14 or PCIFG_H 00h P7IN Port 7 Input Read only Byte undefined Section 8 4 5 or PDIN_L 02h P7OUT Port 7 Output Read write Byte undefined Section 8 4 6 or PDOUT_L 04h P7DIR Port 7 Direction Read write Byte 00h Section 8 4 7 or PDDIR_L 06h P7REN Port 7 Resistor Enable Read write Byte 00h Section 8 4 8 or PDREN_L 0Ah P7...

Page 304: ...on 8 4 13 or PDIE_H 1Dh P8IFG Port 8 Interrupt Flag Read write Byte 00h Section 8 4 14 or PDIFG_H 00h P9IN Port 9 Input Read only Byte undefined Section 8 4 5 or PEIN_L 02h P9OUT Port 9 Output Read write Byte undefined Section 8 4 6 or PEOUT_L 04h P9DIR Port 9 Direction Read write Byte 00h Section 8 4 7 or PEDIR_L 06h P9REN Port 9 Resistor Enable Read write Byte 00h Section 8 4 8 or PEREN_L 0Ah P9...

Page 305: ... 8 4 13 or PEIE_H 1Dh P10IFG Port 10 Interrupt Flag Read write Byte 00h Section 8 4 14 or PEIFG_H 00h P11IN Port 11 Input Read only Byte undefined Section 8 4 5 or PFIN_L 02h P11OUT Port 11 Output Read write Byte undefined Section 8 4 6 or PFOUT_L 04h P11DIR Port 11 Direction Read write Byte 00h Section 8 4 7 or PFDIR_L 06h P11REN Port 11 Resistor Enable Read write Byte 00h Section 8 4 8 or PFREN_...

Page 306: ...ad write Word 0000h 0Ah PASEL0_L Read write Byte 00h 0Bh PASEL0_H Read write Byte 00h 0Ch PASEL1 Port A Select 1 Read write Word 0000h 0Ch PASEL1_L Read write Byte 00h 0Dh PASEL1_H Read write Byte 00h 16h PASELC Port A Complement Select Read write Word 0000h 16h PASELC_L Read write Byte 00h 17h PASELC_H Read write Byte 00h 18h PAIES Port A Interrupt Edge Select Read write Word undefined 18h PAIES_...

Page 307: ...ad write Word 0000h 0Ah PBSEL0_L Read write Byte 00h 0Bh PBSEL0_H Read write Byte 00h 0Ch PBSEL1 Port B Select 1 Read write Word 0000h 0Ch PBSEL1_L Read write Byte 00h 0Dh PBSEL1_H Read write Byte 00h 16h PBSELC Port B Complement Select Read write Word 0000h 16h PBSELC_L Read write Byte 00h 17h PBSELC_H Read write Byte 00h 18h PBIES Port B Interrupt Edge Select Read write Word undefined 18h PBIES_...

Page 308: ...ad write Word 0000h 0Ah PCSEL0_L Read write Byte 00h 0Bh PCSEL0_H Read write Byte 00h 0Ch PCSEL1 Port C Select 1 Read write Word 0000h 0Ch PCSEL1_L Read write Byte 00h 0Dh PCSEL1_H Read write Byte 00h 16h PCSELC Port C Complement Select Read write Word 0000h 16h PCSELC_L Read write Byte 00h 17h PCSELC_H Read write Byte 00h 18h PCIES Port C Interrupt Edge Select Read write Word undefined 18h PCIES_...

Page 309: ...ad write Word 0000h 0Ah PDSEL0_L Read write Byte 00h 0Bh PDSEL0_H Read write Byte 00h 0Ch PDSEL1 Port D Select 1 Read write Word 0000h 0Ch PDSEL1_L Read write Byte 00h 0Dh PDSEL1_H Read write Byte 00h 16h PDSELC Port D Complement Select Read write Word 0000h 16h PDSELC_L Read write Byte 00h 17h PDSELC_H Read write Byte 00h 18h PDIES Port D Interrupt Edge Select Read write Word undefined 18h PDIES_...

Page 310: ...ad write Word 0000h 0Ah PESEL0_L Read write Byte 00h 0Bh PESEL0_H Read write Byte 00h 0Ch PESEL1 Port E Select 1 Read write Word 0000h 0Ch PESEL1_L Read write Byte 00h 0Dh PESEL1_H Read write Byte 00h 16h PESELC Port E Complement Select Read write Word 0000h 16h PESELC_L Read write Byte 00h 17h PESELC_H Read write Byte 00h 18h PEIES Port E Interrupt Edge Select Read write Word undefined 18h PEIES_...

Page 311: ...ad write Word 0000h 0Ah PFSEL0_L Read write Byte 00h 0Bh PFSEL0_H Read write Byte 00h 0Ch PFSEL1 Port F Select 1 Read write Word 0000h 0Ch PFSEL1_L Read write Byte 00h 0Dh PFSEL1_H Read write Byte 00h 16h PFSELC Port F Complement Select Read write Word 0000h 16h PFSELC_L Read write Byte 00h 17h PFSELC_H Read write Byte 00h 18h PFIES Port F Interrupt Edge Select Read write Word undefined 18h PFIES_...

Page 312: ...yte 00h 05h PJDIR_H Read write Byte 00h 06h PJREN Port J Resistor Enable Read write Word 0000h 06h PJREN_L Read write Byte 00h 07h PJREN_H Read write Byte 00h 0Ah PJSEL0 Port J Select 0 Read write Word 0000h 0Ah PJSEL0_L Read write Byte 00h 0Bh PJSEL0_H Read write Byte 00h 0Ch PJSEL1 Port J Select 1 Read write Word 0000h 0Ch PJSEL1_L Read write Byte 00h 0Dh PJSEL1_H Read write Byte 00h 16h PJSELC ...

Page 313: ...Interrupt Flag P1IFG 7 Interrupt Priority Lowest 8 4 2 P2IV Register Port 2 Interrupt Vector Register Figure 8 2 P2IV Register 15 14 13 12 11 10 9 8 P2IV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 P2IV r0 r0 r0 r 0 r 0 r 0 r 0 r0 Table 8 5 P2IV Register Description Bit Field Type Reset Description 15 0 P2IV R 0h Port 2 interrupt vector value 00h No interrupt pending 02h Interrupt Source Port 2 0 inte...

Page 314: ...Interrupt Flag P3IFG 7 Interrupt Priority Lowest 8 4 4 P4IV Register Port 4 Interrupt Vector Register Figure 8 4 P4IV Register 15 14 13 12 11 10 9 8 P4IV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 P4IV r0 r0 r0 r 0 r 0 r 0 r 0 r0 Table 8 7 P4IV Register Description Bit Field Type Reset Description 15 0 P4IV R 0h Port 4 interrupt vector value 00h No interrupt pending 02h Interrupt Source Port 4 0 inte...

Page 315: ...cription 7 0 PxOUT RW Undefined Port x output When I O configured to output mode 0b Output is low 1b Output is high When I O configured to input mode and pullups pulldowns enabled 0b Pulldown selected 1b Pullup selected 8 4 7 PxDIR Register Port x Direction Register Figure 8 7 PxDIR Register 7 6 5 4 3 2 1 0 PxDIR rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 8 10 P1DIR Register Description Bit Fie...

Page 316: ...ach bit position in PxSEL1 and PxSEL0 are combined to specify the function For example if P1SEL1 5 1 and P1SEL0 5 0 then the secondary module function is selected for P1 5 See PxSEL1 for the definition of each value 8 4 10 PxSEL1 Register Port x Function Selection Register 1 Figure 8 10 PxSEL1 Register 7 6 5 4 3 2 1 0 PxSEL1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 8 13 PxSEL1 Register Descri...

Page 317: ...ge Select Register Figure 8 12 PxIES Register 7 6 5 4 3 2 1 0 PxIES rw rw rw rw rw rw rw rw Table 8 15 PxIES Register Description Bit Field Type Reset Description 7 0 PxIES RW Undefined Port x interrupt edge select 0b PxIFG flag is set with a low to high transition 1b PxIFG flag is set with a high to low transition 8 4 13 PxIE Register Port x Interrupt Enable Register Figure 8 13 PxIE Register 7 6...

Page 318: ...rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 8 17 PxIFG Register Description Bit Field Type Reset Description 7 0 PxIFG RW 0h Port x interrupt flag 0b No interrupt is pending 1b Interrupt is pending 318 Digital I O SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 319: ...s chapter describes the operation and use of the CRC module Topic Page 9 1 Cyclic Redundancy Check CRC Module Introduction 320 9 2 CRC Standard and Bit Order 320 9 3 CRC Checksum Generation 321 9 4 CRC Registers 324 319 SLAU272C May 2011 Revised November 2013 CRC Module Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 320: ...n identical signatures when the CRC is initialized with a fixed seed value whereas different sequences of input data in general result in different signatures 9 2 CRC Standard and Bit Order The definitions of the various CRC standards were done in the era of main frame computers and by convention bit 0 was treated as the MSB Today as in most microcontrollers such as the MSP430 bit 0 normally denot...

Page 321: ...lculation has to be started by writing a seed to the CRCINIRES register to initialize the register Software or hardware for example the DMA can transfer data to the CRCDI or CRCDIRB register for example from memory The value in CRCDI or CRCDIRB is then included into the signature and the result is available in the signature result registers at the next read access CRCINIRES and CRCRESR The signatu...

Page 322: ...dress EndAddress MOV EndAddress R5 MOV INIT CRCINIRES INIT to CRCINIRES L1 MOV R4 CRCDI Item to Data In register CMP R5 R4 End address reached JLO L1 No MOV Check_Sum CRCDI Yes Include checksum TST CRCINIRES Result 0 JNZ CRC_ERROR No CRCRES 0 error Yes CRCRES 0 information ok POP R5 Restore registers POP R4 The details of the implemented CRC algorithm are shown by the data sequences in Example 9 2...

Page 323: ... 06F91h jeq Success no error br Error to error handler mov 0FFFFh CRCINIRES initialize CRC mov b 00031h CRCDIRB_L 1 mov b 00032h CRCDIRB_L 2 mov b 00033h CRCDIRB_L 3 mov b 00034h CRCDIRB_L 4 mov b 00035h CRCDIRB_L 5 mov b 00036h CRCDIRB_L 6 mov b 00037h CRCDIRB_L 7 mov b 00038h CRCDIRB_L 8 mov b 00039h CRCDIRB_L 9 cmp 029B1h CRCINIRES compare result CRCRESR contains 08D94h jeq Success no error br ...

Page 324: ...ccess Reset Section 00h CRCDI CRC Data In Read write Word 0000h Section 9 4 1 00h CRCDI_L Read write Byte 00h 01h CRCDI_H Read write Byte 00h 02h CRCDIRB CRC Data In Reverse Byte Read write Word 0000h Section 9 4 2 02h CRCDIRB_L Read write Byte 00h 03h CRCDIRB_H Read write Byte 00h 04h CRCINIRES CRC Initialization and Result Read write Word FFFFh Section 9 4 3 04h CRCINIRES_L Read write Byte FFh 0...

Page 325: ...CRCDIRB Register CRC Data In Reverse Register Figure 9 4 CRCDIRB Register 15 14 13 12 11 10 9 8 CRCDIRB rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 CRCDIRB rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 9 3 CRCDIRB Register Description Bit Field Type Reset Description 15 0 CRCDIRB RW 0h CRC data in reverse byte Data written to the CRCDIRB register is included to the present signature in...

Page 326: ... value written to it The value just written can be read from CRCINIRES register 9 4 4 CRCRESR Register CRC Reverse Result Register Figure 9 6 CRCRESR Register 15 14 13 12 11 10 9 8 CRCRESR r 1 r 1 r 1 r 1 r 1 r 1 r 1 r 1 7 6 5 4 3 2 1 0 CRCRESR r 1 r 1 r 1 r 1 r 1 r 1 r 1 r 1 Table 9 5 CRCRESR Register Description Bit Field Type Reset Description 15 0 CRCRESR R FFFFh CRC reverse result This regist...

Page 327: ...terval timer This chapter describes the watchdog timer The enhanced watchdog timer WDT_A is implemented in all devices Topic Page 10 1 WDT_A Introduction 328 10 2 WDT_A Operation 330 10 3 WDT_A Registers 332 327 SLAU272C May 2011 Revised November 2013 Watchdog Timer WDT_A Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 328: ...re selectable time intervals Watchdog mode Interval mode Password protected access to Watchdog Timer Control WDTCTL register Selectable clock source Can be stopped to conserve power Clock fail safe feature The watchdog timer block diagram is shown in Figure 10 1 NOTE Watchdog timer powers up active After a PUC the WDT_A module is automatically configured in the watchdog mode with an initial approx...

Page 329: ...Pulse Generator VLOCLK Clock Request Logic X_CLK request SMCLK request ACLK request VLOCLK request 10 11 Q9 Q13 Q15 Q19 Q23 Q27 Q31 X_CLK 11 10 01 00 11 10 01 00 0 1 16 bit Counter CLK 32Bit WDT extension www ti com WDT_A Introduction Figure 10 1 Watchdog Timer Block Diagram 329 SLAU272C May 2011 Revised November 2013 Watchdog Timer WDT_A Submit Documentation Feedback Copyright 2011 2013 Texas Ins...

Page 330: ...timer mode the WDTIFG flag is set at the expiration of the selected time interval A PUC is not generated in interval timer mode at expiration of the selected timer interval and the WDTIFG enable bit WDTIE remains unchanged When the WDTIE bit and the GIE bit are set the WDTIFG flag requests an interrupt The WDTIFG interrupt flag is automatically reset when its interrupt request is serviced or may b...

Page 331: ...igured For example the WDT_A should not be configured in watchdog mode with a clock source that is originally sourced from DCO XT1 in high frequency mode or XT2 via SMCLK or ACLK if the user wants to use low power mode 3 In this case SMCLK or ACLK would remain enabled increasing the current consumption of LPM3 When the watchdog timer is not required the WDTHOLD bit can be used to hold the WDTCNT r...

Page 332: ... generic register ANYREG the suffix _L ANYREG_L refers to the lower byte of the register bits 0 through 7 The suffix _H ANYREG_H refers to the upper byte of the register bits 8 through 15 Table 10 1 WDT_A Registers Offset Acronym Register Name Type Access Reset Section 0Ch WDTCTL Watchdog Timer Control Read write Word 6904h Section 10 3 1 0Ch WDTCTL_L Read write Byte 04h 0Dh WDTCTL_H Read write By...

Page 333: ... in data sheet 4 WDTTMSEL RW 0h Watchdog timer mode select 0b Watchdog mode 1b Interval timer mode 3 WDTCNTCL RW 0h Watchdog timer counter clear Setting WDTCNTCL 1 clears the count value to 0000h WDTCNTCL is automatically reset 0b No action 1b WDTCNT 0000h 2 0 WDTIS RW 0h Watchdog timer interval select These bits select the watchdog timer interval to set the WDTIFG flag or generate a PUC 000b Watc...

Page 334: ...er_A modules on a given device see the device specific data sheet This chapter describes the operation and use of the Timer_A module Topic Page 11 1 Timer_A Introduction 335 11 2 Timer_A Operation 337 11 3 Timer_A Registers 349 334 Timer_A SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 335: ...tching Interrupt vector register for fast decoding of all Timer_A interrupts The block diagram of Timer_A is shown in Figure 11 1 NOTE Use of the word count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter an associated action does not take place NOTE Nomenclature Ther...

Page 336: ... ID 00 01 10 11 Clear Timer Clock EQU0 Timer Clock Timer Clock TAxCCR6 SCCI Y A EN CCR1 POR TACLR CCR0 Timer Block 00 01 10 11 Set TAxCCR6 CCIFG CAP 1 0 1 0 CCR2 CCR3 ACLK SMCLK TAxCLK INCLK IDEX Divider 1 8 CCR4 CCR5 2 2 3 2 2 2 3 Timer_A Introduction www ti com Figure 11 1 Timer_A Block Diagram 336 Timer_A SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 ...

Page 337: ... The timer clock can be sourced from ACLK SMCLK or externally via TAxCLK or INCLK The clock source is selected with the TASSEL bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the ID bits The selected clock source can be further divided by 2 3 4 5 6 7 or 8 using the TAIDEX bits The timer clock divider logic is reset when TACLR is set NOTE Timer_A divi...

Page 338: ... of timer counts in the period is TAxCCR0 1 When the timer value equals TAxCCR0 the timer restarts counting from zero If up mode is selected when the timer value is greater than TAxCCR0 the timer immediately restarts counting from zero Figure 11 2 Up Mode The TAxCCR0 CCIFG interrupt flag is set when the timer counts to the TAxCCR0 value The TAIFG interrupt flag is set when the timer counts from TA...

Page 339: ...ode Flag Setting 11 2 3 3 Use of Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TAxCCRn register in the interrupt service routine Figure 11 6 shows two separate time intervals t0 and t1 being added to the capture compare registers In thi...

Page 340: ...he TACLR bit also clears the TAxR value and the timer clock divider In up down mode the TAxCCR0 CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period separated by one half the timer period The TAxCCR0 CCIFG interrupt flag is set when the timer counts from TAxCCR0 1 to TAxCCR0 and TAIFG is set when the timer completes counting down from 0001h to 0000h Figure 11 8 shows...

Page 341: ...f the blocks may be used to capture the timer data or to generate time intervals 11 2 4 1 Capture Mode The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCIS bits The CM bits select the capture ed...

Page 342: ...nputs while in capture mode may cause unintended capture events To avoid this scenario capture inputs should only be changed when capture mode is disabled CM 0 or CAP 0 Overflow logic is provided in each capture compare register to indicate if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 11 11 COV must be reset w...

Page 343: ... 1 Output Modes The output modes are defined by the OUTMOD bits and are described in Table 11 2 The OUTn signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit 0 because EQUn EQU0 Table 11 2 Output Modes OUTMODx Mode Description 000 Output The output signal OUTn is defined by the OUT bit The OUTn signal updates ...

Page 344: ... Timer_A Operation www ti com 11 2 5 1 1 Output Example Timer in Up Mode The OUTn signal is changed when the timer counts up to the TAxCCRn value and rolls from TAxCCR0 to zero depending on the output mode An example is shown in Figure 11 12 using TAxCCR0 and TAxCCR1 Figure 11 12 Output Example Timer in Up Mode 344 Timer_A SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyr...

Page 345: ...www ti com Timer_A Operation 11 2 5 1 2 Output Example Timer in Continuous Mode The OUTn signal is changed when the timer reaches the TAxCCRn and TAxCCR0 values depending on the output mode An example is shown in Figure 11 13 using TAxCCR0 and TAxCCR1 Figure 11 13 Output Example Timer in Continuous Mode 345 SLAU272C May 2011 Revised November 2013 Timer_A Submit Documentation Feedback Copyright 201...

Page 346: ...de An example is shown in Figure 11 14 using TAxCCR0 and TAxCCR2 Figure 11 14 Output Example Timer in Up Down Mode NOTE Switching between output modes When switching between output modes one of the OUTMOD bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output mo...

Page 347: ...errupt Flag 11 2 6 2 TAxIV Interrupt Vector Generator The TAxCCRy CCIFG flags and TAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register TAxIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the TAxIV register see register description This number can be evaluated or added to the ...

Page 348: ...ncy 6 RETI 5 Interrupt handler for TA0IFG TA0CCR1 through TA0CCR6 CCIFG TA0_HND Interrupt latency 6 ADD TA0IV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG_1_HND Vector 2 TA0CCR1 2 JMP CCIFG_2_HND Vector 4 TA0CCR2 2 JMP CCIFG_3_HND Vector 6 TA0CCR3 2 JMP CCIFG_4_HND Vector 8 TA0CCR4 2 JMP CCIFG_5_HND Vector 10 TA0CCR5 2 JMP CCIFG_6_HND Vector 12 TA0CCR6 2 TA0IFG_HND Vector 1...

Page 349: ...mpare Control 5 Read write Word 0000h Section 11 3 3 0Eh TAxCCTL6 Timer_Ax Capture Compare Control 6 Read write Word 0000h Section 11 3 3 10h TAxR Timer_Ax Counter Read write Word 0000h Section 11 3 2 12h TAxCCR0 Timer_Ax Capture Compare 0 Read write Word 0000h Section 11 3 4 14h TAxCCR1 Timer_Ax Capture Compare 1 Read write Word 0000h Section 11 3 4 16h TAxCCR2 Timer_Ax Capture Compare 2 Read wri...

Page 350: ...W 0h Mode control Setting MCx 00h when Timer_A is not in use conserves power 00b Stop mode Timer is halted 01b Up mode Timer counts up to TAxCCR0 10b Continuous mode Timer counts up to 0FFFFh 11b Up down mode Timer counts up to TAxCCR0 then down to 0000h 3 Reserved RW 0h Reserved 2 TACLR RW 0h Timer_A clear Setting this bit resets TAxR the timer clock divider logic and the count direction The TACL...

Page 351: ...0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 TAxR rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 11 5 TAxR Register Description Bit Field Type Reset Description 15 0 TAxR RW 0h Timer_A register The TAxR register is the count of Timer_A 351 SLAU272C May 2011 Revised November 2013 Timer_A Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 352: ...gnal with the timer clock 0b Asynchronous capture 1b Synchronous capture 10 SCCI RW 0h Synchronized capture compare input The selected CCI input signal is latched with the EQUx signal and can be read via this bit 9 Reserved R 0h Reserved Reads as 0 8 CAP RW 0h Capture mode 0b Compare mode 1b Capture mode 7 5 OUTMOD RW 0h Output mode Modes 2 3 6 and 7 are not useful for TAxCCR0 because EQUx EQU0 00...

Page 353: ...indicates a capture overflow occurred COV must be reset with software 0b No capture overflow occurred 1b Capture overflow occurred 0 CCIFG RW 0h Capture compare interrupt flag 0b No interrupt pending 1b Interrupt pending 353 SLAU272C May 2011 Revised November 2013 Timer_A Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 354: ... r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 TAIV r0 r0 r0 r0 r 0 r 0 r 0 r0 Table 11 8 TAxIV Register Description Bit Field Type Reset Description 15 0 TAIV R 0h Timer_A interrupt vector value 00h No interrupt pending 02h Interrupt Source Capture compare 1 Interrupt Flag TAxCCR1 CCIFG Interrupt Priority Highest 04h Interrupt Source Capture compare 2 Interrupt Flag TAxCCR2 CCIFG 06h Interrupt Source Capture...

Page 355: ...reset of the timer divider logic Table 11 9 TAxEX0 Register Description Bit Field Type Reset Description 15 3 Reserved R 0h Reserved Reads as 0 2 0 TAIDEX RW 0h Input divider expansion These bits along with the ID bits select the divider for the input clock 000b Divide by 1 001b Divide by 2 010b Divide by 3 011b Divide by 4 100b Divide by 5 101b Divide by 6 110b Divide by 7 111b Divide by 8 355 SL...

Page 356: ...imer_B modules on a given device see the device specific data sheet This chapter describes the operaand use of the Timer_B module Topic Page 12 1 Timer_B Introduction 357 12 2 Timer_B Operation 359 12 3 Timer_B Registers 372 356 Timer_B SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 357: ...is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter an associated action does not take place NOTE Nomenclature There may be multiple instantiations of Timer_B on a given device The prefix TBx is used where x is a greater than equal to zero indicating the Timer_B instantiation F...

Page 358: ...xCCR6 RC 10 12 16 8 TBCLGRP CCR5 CCR4 CCR1 Group Load Logic Group Load Logic TBSSEL 00 01 10 11 GND VCC CCI6A CCI6B 00 01 10 11 CCIS 00 01 10 11 00 01 10 11 CAP 1 0 SCS 1 0 Set TBxCCR6 CCIFG Compare Latch TBxCL6 ACLK SMCLK TBxCLK INCLK Timer Clock Divider 1 2 4 8 ID IDEX Divider 1 8 2 2 3 2 2 2 2 2 2 3 Timer_B Introduction www ti com Figure 12 1 Timer_B Block Diagram 358 Timer_B SLAU272C May 2011 ...

Page 359: ...FFh respectively Data written to the TBxR register in 8 10 and 12 bit mode is right justified with leading zeros 12 2 1 2 Clock Source Select and Divider The timer clock can be sourced from ACLK SMCLK or externally via TBxCLK or INCLK The clock source is selected with the TBSSEL bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the ID bits The selected...

Page 360: ... 2 The number of timer counts in the period is TBxCL0 1 When the timer value equals TBxCL0 the timer restarts counting from zero If up mode is selected when the timer value is greater than TBxCL0 the timer immediately restarts counting from zero Figure 12 2 Up Mode The TBxCCR0 CCIFG interrupt flag is set when the timer counts to the TBxCL0 value The TBIFG interrupt flag is set when the timer count...

Page 361: ...re 12 5 Continuous Mode Flag Setting 12 2 3 3 Use of Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TBxCLn latch in the interrupt service routine Figure 12 6 shows two separate time intervals t0 and t1 being added to the capture compare ...

Page 362: ... TBxR max to zero Figure 12 7 Up Down Mode The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TBCLR bit must be used to clear the direction The TBCLR bit also clears the TBxR value and the timer clock divider In up down mode the TBxCCR0 CCIFG interrupt flag and the TBIFG interr...

Page 363: ...ctive ttimer Cycle time of the timer clock TBxCLn Content of compare latch n The ability to simultaneously load grouped compare latches ensures the dead times Figure 12 9 Output Unit in Up Down Mode 12 2 4 Capture Compare Blocks Up to seven identical capture compare blocks TBxCCRn where n 0 to 6 are present in Timer_B Any of the blocks may be used to capture the timer data or to generate time inte...

Page 364: ...he timer clock is recommended see Figure 12 10 Figure 12 10 Capture Signal SCS 1 NOTE Changing Capture Inputs Changing capture inputs while in capture mode may cause unintended capture events To avoid this scenario capture inputs should only be changed when capture mode is disabled CM 0 or CAP 0 Overflow logic is provided in each capture compare register to indicate if a second capture was perform...

Page 365: ...ording to the output mode 12 2 4 2 1 Compare Latch TBxCLn The TBxCCRn compare latch TBxCLn holds the data for the comparison to the timer value in compare mode TBxCLn is buffered by TBxCCRn The buffered compare latch gives the user control over when a compare period updates The user cannot directly access TBxCLn Compare data is written to each TBxCCRn and automatically transferred to TxBCLn The ti...

Page 366: ...ing PSEL bit is set and port configured as input and when the pin is pulled high all Timer_B outputs are in a high impedance state 12 2 5 1 Output Modes The output modes are defined by the OUTMOD bits and are described in Table 12 4 The OUTn signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit 0 because EQUn E...

Page 367: ...ts www ti com Timer_B Operation 12 2 5 1 1 Output Example Timer in Up Mode The OUTn signal is changed when the timer counts up to the TBxCLn value and rolls from TBxCL0 to zero depending on the output mode An example is shown in Figure 12 12 using TBxCL0 and TBxCL1 Figure 12 12 Output Example Timer in Up Mode 367 SLAU272C May 2011 Revised November 2013 Timer_B Submit Documentation Feedback Copyrig...

Page 368: ... Timer_B Operation www ti com 12 2 5 1 2 Output Example Timer in Continuous Mode The OUTn signal is changed when the timer reaches the TBxCLn and TBxCL0 values depending on the output mode An example is shown in Figure 12 13 using TBxCL0 and TBxCL1 Figure 12 13 Output Example Timer in Continuous Mode 368 Timer_B SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2...

Page 369: ...ode An example is shown in Figure 12 14 using TBxCL0 and TBxCL3 Figure 12 14 Output Example Timer in Up Down Mode NOTE Switching between output modes When switching between output modes one of the OUTMOD bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output mod...

Page 370: ... TBxIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer_B interrupts do not affect the TBxIV value Any access read or write of the TBxIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after...

Page 371: ...MP CCIFG_5_HND Vector 10 TB0CCR5 2 JMP CCIFG_6_HND Vector 12 TB0CCR6 2 TB0IFG_HND Vector 14 TB0IFG Flag Task starts here RETI 5 CCIFG_6_HND Vector 12 TB0CCR6 Task starts here RETI Back to main program 5 CCIFG_5_HND Vector 10 TB0CCR5 Task starts here RETI Back to main program 5 CCIFG_4_HND Vector 8 TB0CCR4 Task starts here RETI Back to main program 5 CCIFG_3_HND Vector 6 TB0CCR3 Task starts here RE...

Page 372: ...ure Compare Control 5 Read write Word 0000h Section 12 3 3 0Eh TBxCCTL6 Timer_B Capture Compare Control 6 Read write Word 0000h Section 12 3 3 10h TBxR Timer_B Counter Read write Word 0000h Section 12 3 2 12h TBxCCR0 Timer_B Capture Compare 0 Read write Word 0000h Section 12 3 4 14h TBxCCR1 Timer_B Capture Compare 1 Read write Word 0000h Section 12 3 4 16h TBxCCR2 Timer_B Capture Compare 2 Read wr...

Page 373: ... length 00b 16 bit TBxR max 0FFFFh 01b 12 bit TBxR max 0FFFh 10b 10 bit TBxR max 03FFh 11b 8 bit TBxR max 0FFh 10 Reserved R 0h Reserved Always reads as 0 9 8 TBSSEL RW 0h Timer_B clock source select 00b TBxCLK 01b ACLK 10b SMCLK 11b INCLK 7 6 ID RW 0h Input divider These bits along with the TBIDEX bits select the divider for the input clock 00b 1 01b 2 10b 4 11b 8 5 4 MC RW 0h Mode control Settin...

Page 374: ...ption continued Bit Field Type Reset Description 0 TBIFG RW 0h Timer_B interrupt flag 0b No interrupt pending 1b Interrupt pending 374 Timer_B SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 375: ...0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 TBxR rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 12 7 TBxR Register Description Bit Field Type Reset Description 15 0 TBxR RW 0h Timer_B register The TBxR register is the count of Timer_B 375 SLAU272C May 2011 Revised November 2013 Timer_B Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 376: ...clock 0b Asynchronous capture 1b Synchronous capture 10 9 CLLD RW 0h Compare latch load These bits select the compare latch load event 00b TBxCLn loads on write to TBxCCRn 01b TBxCLn loads when TBxR counts to 0 10b TBxCLn loads when TBxR counts to 0 up or continuous mode TBxCLn loads when TBxR counts to TBxCL0 or to 0 up down mode 11b TBxCLn loads when TBxR counts to TBxCLn 8 CAP RW 0h Capture mod...

Page 377: ... low 1b Output high 1 COV RW 0h Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0b No capture overflow occurred 1b Capture overflow occurred 0 CCIFG RW 0h Capture compare interrupt flag 0b No interrupt pending 1b Interrupt pending 377 SLAU272C May 2011 Revised November 2013 Timer_B Submit Documentation Feedback Copyright 2011 2013 Texas Instruments I...

Page 378: ...le 12 9 TBxCCRn Register Description Bit Field Type Reset Description 15 0 TBxCCRn RW 0h Timer_B capture compare register Compare mode TBxCCRn holds the data for the comparison to the timer value in the Timer_B Register TBR Capture mode The Timer_B Register TBR is copied into the TBxCCRn register when a capture is performed 378 Timer_B SLAU272C May 2011 Revised November 2013 Submit Documentation F...

Page 379: ...rrupt Flag TBxCCR1 CCIFG Interrupt Priority Highest 04h Interrupt Source Capture compare 2 Interrupt Flag TBxCCR2 CCIFG 06h Interrupt Source Capture compare 3 Interrupt Flag TBxCCR3 CCIFG 08h Interrupt Source Capture compare 4 Interrupt Flag TBxCCR4 CCIFG 0Ah Interrupt Source Capture compare 5 Interrupt Flag TBxCCR5 CCIFG 0Ch Interrupt Source Capture compare 6 Interrupt Flag TBxCCR6 CCIFG 0Eh Inte...

Page 380: ...t of the timer divider logic Table 12 11 TBxEX0 Register Description Bit Field Type Reset Description 15 3 Reserved R 0h Reserved Always reads as 0 2 0 TBIDEX RW 0h Input divider expansion These bits along with the ID bits select the divider for the input clock 000b Divide by 1 001b Divide by 2 010b Divide by 3 011b Divide by 4 100b Divide by 5 101b Divide by 6 110b Divide by 7 111b Divide by 8 38...

Page 381: ...calendar mode and not counter mode The RTC_B also support operation in LPMx 5 See the device specific data sheet for the supported features This chapter describes the RTC_B module Topic Page 13 1 Real Time Clock RTC_B Introduction 382 13 2 RTC_B Operation 384 13 3 RTC_B Registers 389 381 SLAU272C May 2011 Revised November 2013 Real Time Clock B RTC_B Submit Documentation Feedback Copyright 2011 20...

Page 382: ...at is available in some other RTC modules is not supported Interrupt capability Selectable BCD or binary format Programmable alarms Calibration logic for time offset correction Operation in LPMx 5 The RTC_B block diagram for devices supporting LPMx 5 is shown in Figure 13 1 NOTE Real time clock initialization Most RTC_B module registers have no initial condition These registers must be configured ...

Page 383: ...0 011 010 001 000 3 RT0IP RTCHOLD Keepout Logic Set_RTCRDYIFG Calibration Logic 5 RTCCALS RTCCAL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 111 hour changed midnight noon RTCHOUR RTCMIN RTCSEC 110 101 100 011 010 001 000 111 from 32kHz Crystal Osc www ti com Real Time Clock RTC_B Introduction Figure 13 1 RTC_B Block Diagram 383 SLAU272C May 2011 Revised November 2013 Real Time Clock B RTC_B Submit Documentation Feed...

Page 384: ...registers the alarm is enabled When enabled the RTCAIFG is set when the count transitions from 00 14 59 to 00 15 00 01 14 59 to 01 15 00 02 14 59 to 02 15 00 and so on Example 2 A user wishes to set an alarm every day at 04 00 00 This is possible by setting RTCAHOUR to 4 By setting the AE bit of the RTCHOUR and clearing all other AE bits of the alarm registers the alarm is enabled When enabled the...

Page 385: ...ters When the counter clock is asynchronous to the CPU clock any read from any RTCSEC RTCMIN RTCHOUR RTCDOW RTCDAY RTCMON or RTCYEAR register while the RTCRDY is reset may result in invalid data being read To safely read the counting registers either polling of the RTCRDY bit or the synchronization procedure previously described can be used Alternatively the counter register can be read multiple t...

Page 386: ...terval bits RT0IP or RT1IP while the corresponding pre scaler is running or is stopped in a non zero state can result in setting the corresponding interrupt flags The RTCOFIFG bit flags a failure of the 32 kHz crystal oscillator Its main purpose is to wake up the CPU from LPM3 5 if an oscillator failure occurs 13 2 4 1 RTCIV Software Example The following software example shows the recommended use...

Page 387: ...y adjustment of approximately 2 ppm or 4 ppm respectively To calibrate the frequency the RTCCLK output signal is available at a pin RTCCALF bits can be used to select the frequency rate of the output signal either no signal 512 Hz 256 Hz or 1 Hz The basic flow to calibrate the frequency is as follows 1 Configure the RTCCLK pin 2 Measure the RTCCLK output signal with an appropriate resolution frequ...

Page 388: ...lly configure input interrupt pins for wake up Configure RTC_B interrupts for wake up set RTCTEVIE RTCAIE RT1PSIE or RTCOFIE If the alarm interrupt is also used as wake up event the alarm registers must be configured as needed 2 Enter LPMx 5 with LPMx 5 entry sequence MOV PMMKEY PMMREGOFF PMMCTL0 Open PMM registers for write and set PMMREGOFF BIS LPM4 SR Enter LPMx 5 when PMMREGOFF is set 3 LOCKLP...

Page 389: ...L23_H 08h RTCPS0CTL Real Time Prescale Timer 0 Control Read write Word 0000h not retained 08h RTCPS0CTLL Read write Byte 00h not retained or RTCPS0CTL_L 09h RTCPS0CTLH Read write Byte 00h not retained or RTCPS0CTL_H 0Ah RTCPS1CTL Real Time Prescale Timer 1 Control Read write Word 0000h not retained 0Ah RTCPS1CTLL Read write Byte 00h not retained or RTCPS1CTL_L 0Bh RTCPS0CTLH Read write Byte 00h no...

Page 390: ...te undefined retained or RTCAMINHR_L 19h RTCAHOUR Real Time Clock Hours Alarm Read write Byte undefined retained or RTCAMINHR_H 1Ah RTCADOWDAY Real Time Clock Day of Week Day of Read write Word undefined retained Month Alarm 1Ah RTCADOW Real Time Clock Day of Week Alarm Read write Byte undefined retained or RTCADOWDAY_L 1Bh RTCADAY Real Time Clock Day of Month Alarm Read write Byte undefined retai...

Page 391: ...Real time clock alarm interrupt enable In modules supporting LPMx 5 this interrupt can be used as LPMx 5 wake up event 0b Interrupt not enabled 1b Interrupt enabled LPMx 5 wake up enabled 4 RTCRDYIE RW 0h Real time clock ready interrupt enable 0b Interrupt not enabled 1b Interrupt enabled 3 RTCOFIFG RW 0h 32 kHz crystal oscillator fault interrupt flag This interrupt can be used as LPMx 5 wake up e...

Page 392: ...y hexadecimal code selected 1b BCD Binary coded decimal BCD code selected 6 RTCHOLD RW 1h Real time clock hold 0b Real time clock is operational 1b The calendar is stopped as well as the prescale counters RT0PS and RT1PS 5 Reserved R 1h Reserved Always read as 1 4 RTCRDY RW 1h Real time clock ready 0b RTC time values in transition 1b RTC time values safe for reading This bit indicates when the rea...

Page 393: ...RTCCALS 0 adjustment in frequency 13 3 4 RTCCTL3 Register Real Time Clock Control 3 Register Figure 13 5 RTCCTL3 Register 7 6 5 4 3 2 1 0 Reserved RTCCALFx r0 r0 r0 r0 r0 r0 rw 0 rw 0 Table 13 5 RTCCTL3 Register Description Bit Field Type Reset Description 7 2 Reserved R 0h Reserved Always read as 0 1 0 RTCCALFx RW 0h Real time clock calibration frequency Selects frequency output to RTCCLK pin for...

Page 394: ... Register BCD Format Real Time Clock Seconds Register BCD Format Figure 13 7 RTCSEC Register 7 6 5 4 3 2 1 0 0 Seconds high digit Seconds low digit r 0 rw rw rw rw rw rw rw Table 13 7 RTCSEC Register Description Bit Field Type Reset Description 7 0 R 0h Always reads as 0 6 4 Seconds high digit RW undefined Seconds high digit Valid values are 0 to 5 3 0 Seconds low digit RW undefined Seconds low di...

Page 395: ... Register BCD Format Real Time Clock Minutes Register BCD Format Figure 13 9 RTCMIN Register 7 6 5 4 3 2 1 0 0 Minutes high digit Minutes low digit r 0 rw rw rw rw rw rw rw Table 13 9 RTCMIN Register Description Bit Field Type Reset Description 7 0 R 0h Always reads as 0 6 4 Minutes high digit RW undefined Minutes high digit Valid values are 0 to 5 3 0 Minutes low digit RW undefined Minutes low di...

Page 396: ...HOUR Register BCD Format Real Time Clock Hours Register BCD Format Figure 13 11 RTCHOUR Register 7 6 5 4 3 2 1 0 0 0 Hours high digit Hours low digit r 0 r 0 rw rw rw rw rw rw Table 13 11 RTCHOUR Register Description Bit Field Type Reset Description 7 6 0 R 0h Always reads as 0 5 4 Hours high digit RW undefined Hours high digit Valid values are 0 to 2 3 0 Hours low digit RW undefined Hours low dig...

Page 397: ...escription Bit Field Type Reset Description 7 5 0 R 0h Always reads as 0 4 0 Day of month RW undefined Day of month Valid values are 1 to 31 13 3 13 RTCDAY Register BCD Format Real Time Clock Day of Month Register BCD Format Figure 13 14 RTCDAY Register 7 6 5 4 3 2 1 0 0 0 Day of month high digit Day of month low digit r 0 r 0 rw rw rw rw rw rw Table 13 14 RTCDAY Register Description Bit Field Typ...

Page 398: ... 15 RTCMON Register BCD Format Real Time Clock Month Register Figure 13 16 RTCMON Register 7 6 5 4 3 2 1 0 0 0 0 Month high Month low digit digit r 0 r 0 r 0 rw rw rw rw rw Table 13 16 RTCMON Register Description Bit Field Type Reset Description 7 5 0 R 0h Always reads as 0 4 Month high digit RW undefined Month high digit Valid values are 0 or 1 3 0 Month low digit RW undefined Month low digit Val...

Page 399: ...CD Format Real Time Clock Year Register BCD Format Figure 13 18 RTCYEAR Register 15 14 13 12 11 10 9 8 0 Century high digit Century low digit r 0 rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Decade Year lowest digit rw rw rw rw rw rw rw rw Table 13 18 RTCYEAR Register Description Bit Field Type Reset Description 15 0 R 0h Always reads as 0 14 12 Century high digit RW undefined Century high digit Valid val...

Page 400: ...13 3 19 RTCAMIN Register BCD Format Real Time Clock Minutes Alarm Register BCD Format Figure 13 20 RTCAMIN Register 7 6 5 4 3 2 1 0 AE Minutes high digit Minutes low digit rw rw rw rw rw rw rw rw Table 13 20 RTCAMIN Register Description Bit Field Type Reset Description 7 AE RW undefined Alarm enable 0b This alarm register is enabled 1b This alarm register is disabled 6 4 Minutes high digit RW unde...

Page 401: ...CAHOUR Register BCD Format Real Time Clock Hours Alarm Register BCD Format Figure 13 22 RTCAHOUR Register 7 6 5 4 3 2 1 0 AE 0 Hours high digit Hours low digit rw r 0 rw rw rw rw rw rw Table 13 22 RTCAHOUR Register Description Bit Field Type Reset Description 7 AE RW undefined Alarm enable 0b This alarm register is enabled 1b This alarm register is disabled 6 0 R 0h Always reads as 0 5 4 Hours hig...

Page 402: ... RTCADOW Register Description Bit Field Type Reset Description 7 AE RW undefined Alarm enable 0b This alarm register is enabled 1b This alarm register is disabled 6 3 0 R 0h Always reads as 0 2 0 Day of week RW undefined Day of week Valid values are 0 to 6 402 Real Time Clock B RTC_B SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorpo...

Page 403: ...ster BCD Format Real Time Clock Day of Month Alarm Register BCD Format Figure 13 25 RTCADAY Register 7 6 5 4 3 2 1 0 AE 0 Day of month high digit Day of month low digit rw r 0 rw rw rw rw rw rw Table 13 25 RTCADAY Register Description Bit Field Type Reset Description 7 AE RW undefined Alarm enable 0b This alarm register is enabled 1b This alarm register is disabled 6 0 R 0h Always reads as 0 5 4 D...

Page 404: ... is required Table 13 26 RTCPS0CTL Register Description Bit Field Type Reset Description 15 5 Reserved R 0h Reserved Always reads as 0 4 2 RT0IPx RW 0h Prescale timer 0 interrupt interval 000b Divide by 2 001b Divide by 4 010b Divide by 8 011b Divide by 16 100b Divide by 32 101b Divide by 64 110b Divide by 128 111b Divide by 256 1 RT0PSIE RW 0h Prescale timer 0 interrupt enable 0b Interrupt not en...

Page 405: ...iption Bit Field Type Reset Description 15 5 Reserved R 0h Reserved Always reads as 0 4 2 RT1IPx RW 0h Prescale timer 1 interrupt interval 000b Divide by 2 001b Divide by 4 010b Divide by 8 011b Divide by 16 100b Divide by 32 101b Divide by 64 110b Divide by 128 111b Divide by 256 1 RT1PSIE RW 0h Prescale timer 1 interrupt enable 0b Interrupt not enabled 1b Interrupt enabled LPMx 5 wake up enabled...

Page 406: ...ndefined Prescale timer 0 counter value 13 3 28 RTCPS1 Register Real Time Clock Prescale Timer 1 Counter Register Figure 13 29 RTCPS1 Register 7 6 5 4 3 2 1 0 RT1PS rw rw rw rw rw rw rw rw Table 13 29 RTCPS1 Register Description Bit Field Type Reset Description 7 0 RT1PS RW undefined Prescale timer 1 counter value 406 Real Time Clock B RTC_B SLAU272C May 2011 Revised November 2013 Submit Documenta...

Page 407: ... Interrupt Source RTC ready Interrupt Flag RTCRDYIFG Interrupt Priority Highest 04h Interrupt Source RTC interval timer Interrupt Flag RTCTEVIFG 06h Interrupt Source RTC user alarm Interrupt Flag RTCAIFG 08h Interrupt Source RTC prescaler 0 Interrupt Flag RT0PSIFG 0Ah Interrupt Source RTC prescaler 1 Interrupt Flag RT1PSIFG 0Ch Interrupt Source RTC oscillator failure Interrupt Flag RTCOFIFG 0Eh Re...

Page 408: ...rite 12 bit binary number to be converted 13 3 31 BCD2BIN Register BCD to Binary Conversion Register Figure 13 32 BCD2BIN Register 15 14 13 12 11 10 9 8 BCD2BINx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 BCD2BINx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 13 32 BCD2BIN Register Description Bit Field Type Reset Description 15 0 BCD2BINx RW 0h Read 12 bit binary conversion of previo...

Page 409: ...iplier MPY32 The MPY32 module is implemented in all devices Topic Page 14 1 32 Bit Hardware Multiplier MPY32 Introduction 410 14 2 MPY32 Operation 412 14 3 MPY32 Registers 424 409 SLAU272C May 2011 Revised November 2013 32 Bit Hardware Multiplier MPY32 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 410: ...e MPY32 supports Unsigned multiply Signed multiply Unsigned multiply accumulate Signed multiply accumulate 8 bit 16 bit 24 bit and 32 bit operands Saturation Fractional numbers 8 bit and 16 bit operation compatible with 16 bit hardware multiplier 8 bit and 24 bit multiplications without requiring a sign extend instruction The MPY32 block diagram is shown in Figure 14 1 410 32 Bit Hardware Multipli...

Page 411: ...S3 SUMEXT 31 0 15 16 31 0 32 bit Demultiplexer 32 bit Multiplexer 16 bit Multiplexer 16 bit Multiplexer OP1_32 OP2_32 MPYMx MPYSAT MPYFRAC MPYC 2 Control Logic OP1 low word www ti com 32 Bit Hardware Multiplier MPY32 Introduction Figure 14 1 MPY32 Block Diagram 411 SLAU272C May 2011 Revised November 2013 32 Bit Hardware Multiplier MPY32 Submit Documentation Feedback Copyright 2011 2013 Texas Instr...

Page 412: ...ult When using indirect addressing for the result a NOP is required before the result is ready The result of a 24 bit or 32 bit operation can be read with successive instructions after writing OP2 or OP2H starting with RES0 except when using an indirect addressing mode to access the result When using indirect addressing for the result a NOP is required before the result is ready Table 14 1 summari...

Page 413: ...tiply accumulate operand bits 16 up to 31 MACS32L Signed multiply accumulate operand bits 0 up to 15 MACS32H Signed multiply accumulate operand bits 16 up to 31 Writing the second operand to the OP2 initiates the multiply operation Writing OP2 starts the selected operation with a 16 bit wide second operand together with the values stored in OP1 Writing OP2L starts the selected operation with a 32 ...

Page 414: ...operation is accessible via RESLO RESHI and SUMEXT In this case the result low register RESLO holds the lower 16 bits of the calculation result and the result high register RESHI holds the upper 16 bits RES0 and RES1 are identical to RESLO and RESHI respectively in usage and access of calculated results The sum extension register SUMEXT contents depend on the multiply operation and are listed in T...

Page 415: ...ord registers when using the labels from the standard definitions file There is no sign extension necessary in software Accessing the multiplier with a byte instruction during a signed operation automatically causes a sign extension of the byte within the multiplier module 32x32 Unsigned Multiply MOV 01234h MPY32L Load low word of 1st operand MOV 01234h MPY32H Load high word of 1st operand MOV 056...

Page 416: ... fractional numbers using the default multiplication mode with MPYFRAC 0 and MPYSAT 0 gives a result with two sign bits For example if two 16 bit Q15 numbers are multiplied a 32 bit result in Q30 format is obtained To convert the result into Q15 format manually the first 15 trailing bits and the extended sign bit must be removed However when the fractional mode of the multiplier is used the redund...

Page 417: ...use The actual content of the result registers is not modified when MPYSAT 1 When the result is accessed using software the value is automatically adjusted to provide the most positive or most negative result when an overflow or underflow has occurred The adjusted result is also used for successive multiply and accumulate operations This allows user software to switch between reading the saturated...

Page 418: ...unshifted RES1 bit15 0 MPYFRAC 1 Unshifted RES1 bit 15 0 and bit 14 1 Unshifted RES1 bit 15 1 and bit 14 0 MPY32 Operation www ti com Table 14 6 Result Availability in Saturation Mode MPYSAT 1 Result Ready in MCLK Cycles Operation After OP1 OP2 RES0 RES1 RES2 RES3 MPYC Bit 8 16 8 16 3 3 N A N A 3 OP2 written 24 32 8 16 7 7 7 7 7 OP2 written 8 16 24 32 7 7 7 7 7 OP2L written 4 4 4 4 4 OP2H written ...

Page 419: ...on MOV B 012h OP2_B Start 16x16 bit operation MOV RES0 R6 R6 0FFFFh MOV RES1 R7 R7 07FFFh The result is saturated because already the result not converted into a fractional number shows an overflow The multiplication of the two positive numbers 00050h and 00012h gives 005A0h 005A0h added to 07FFF FA60h results in 8000 059Fh without MPYC being set Because the MSB of the unmodified result RES1 is 1 ...

Page 420: ... 00000h RES1 00000h RES0 00000h Yes No Yes No MPYFRAC 1 non fractional 64 bit Saturation MPYSAT 1 Yes No Yes No Shift64bit result Calculate SUMEXTbased on MPYC and bit15 of unshifted RES3 Perform 16 16 MAC or MACS Operation Perform MAC or MACS Operation Perform MPY or MPYS Operation MAC or MACS 32 bit Saturation 64 bit Saturation MPY32 Operation www ti com Figure 14 5 Multiplication Flow Chart 420...

Page 421: ...eration was started the carry bit MPYC was 0 from the previous operation but the MSB in result register RES1 is set As one can see in the flow chart the content of the result registers are saturated for multiply and accumulate operations after starting a new operation based on the previous results but depending on the size of the result 32 bit or 64 bit of the newly initiated operation The saturat...

Page 422: ...of 1st operand MOV OPER1H MPY32H Load high word of 1st operand MOV OPER2 OP2 Load 2nd operand 16 bits NOP Need one cycle MOV R5 xxx Move RES0 NOP Need one additional cycle MOV R5 xxx Move RES1 No additional cycles required MOV R5 xxx Move RES2 14 2 7 Using Interrupts If an interrupt occurs after writing OP but before writing OP2 and the multiplier is used in servicing that interrupt the original m...

Page 423: ...outines POP OP2L Restore operand 2 low word POP OP2H Restore operand 2 high word Starts dummy multiplication but result is overwritten by following restore operations POP MPY32L Restore operand 1 low word POP MPY32H Restore operand 1 high word POP RES0 Restore result 0 POP RES1 Restore result 1 POP RES2 Restore result 2 POP RES3 Restore result 3 POP MPY32CTL0 Restore multiplier mode etc reti End o...

Page 424: ...6h MACS_B 8 bit operand one signed multiply accumulate Read write Byte Undefined 08h OP2 16 bit operand two Read write Word Undefined 08h OP2_L Read write Byte Undefined 09h OP2_H Read write Byte Undefined 08h OP2_B 8 bit operand two Read write Byte Undefined 0Ah RESLO 16x16 bit result low word Read write Word Undefined 0Ah RESLO_L Read write Byte Undefined 0Ch RESHI 16x16 bit result high word Rea...

Page 425: ...OP2H_B 24 bit operand 2 high byte Read write Byte Undefined 24h RES0 32x32 bit result 0 least significant word Read write Word Undefined 24h RES0_L Read write Byte Undefined 26h RES1 32x32 bit result 1 Read write Word Undefined 28h RES2 32x32 bit result 2 Read write Word Undefined 2Ah RES3 32x32 bit result 3 most significant word Read write Word Undefined 2Ch MPY32CTL0 MPY32 control register 0 Rea...

Page 426: ...s are delayed 7 MPYOP2_32 RW 0h Multiplier bit width of operand 2 0b 16 bits 1b 32 bits 6 MPYOP1_32 RW 0h Multiplier bit width of operand 1 0b 16 bits 1b 32 bits 5 4 MPYMx RW 0h Multiplier mode 00b MPY Multiply 01b MPYS Signed multiply 10b MAC Multiply accumulate 11b MACS Signed multiply accumulate 3 MPYSAT RW 0h Saturation mode 0b Saturation mode disabled 1b Saturation mode enabled 2 MPYFRAC RW 0...

Page 427: ...systems available on a given device such as digital to analog converters analog to digital converters or comparators This chapter describes the REF module Topic Page 15 1 REF Introduction 428 15 2 Principle of Operation 429 15 3 REF Registers 431 427 SLAU272C May 2011 Revised November 2013 REF Module Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 428: ... are derived by unity or noninverting gain stages The REF module consists of the bandgap and a noninverting buffer stage that generates the three voltage reference available in the system namely 1 5 V 2 0 V and 2 5 V In addition when requested a buffered bandgap voltage is also available Features of the REF include Centralized factory trimmed bandgap with excellent PSRR temperature coefficient and...

Page 429: ... requesting sampled mode In other words static mode always has higher priority over sampled mode 15 2 2 REFCTL The REFCTL registers provide a way to control the reference system from one centralized set of registers REFCTL is used to control the reference system Table 15 1 summarizes the REFCTL bits and their effect on the REF module Table 15 1 REF Control of Reference System REFMSTR 1 Default REF...

Page 430: ...andgap to operate in static mode The BGMODE bit can be used as an indicator of static or sampled mode of operation 15 2 3 1 REFBGACT REFGENACT REFGENBUSY Any module that is using the variable reference line causes REFGENACT to be set inside the REFCTL register This bit is read only and indicates to the user that the REFGEN is active or off Similarly the REFBGACT is active any time one or more modu...

Page 431: ...L ANYREG_L refers to the lower byte of the register bits 0 through 7 The suffix _H ANYREG_H refers to the upper byte of the register bits 8 through 15 Table 15 2 REF Registers Offset Acronym Register Name Type Access Reset Section 00h REFCTL0 REFCTL0 Read write Word 0000h Section 15 3 1 00h REFCTL0_L Read write Byte 80h 01h REFCTL0_H Read write Byte 00h 431 SLAU272C May 2011 Revised November 2013 ...

Page 432: ... Reference generator active 0b Reference generator not active 1b Reference generator active 7 6 Reserved R 0h Reserved Always reads as 0 5 4 REFVSEL RW 0h Reference voltage level select Can be modified only when REFGENBUSY 0 00b 1 5 V available when reference requested or REFON 1 01b 2 0 V available when reference requested or REFON 1 10b 2 5 V available when reference requested or REFON 1 11b 2 5...

Page 433: ...g to digital converter ADC This chapter describes the operation of the ADC10_B module Topic Page 16 1 ADC10_B Introduction 434 16 2 ADC10_B Operation 436 16 3 ADC10_B Registers 449 433 SLAU272C May 2011 Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 434: ...e or external reference Twelve individually configurable external input channels Conversion channel for temperature sensor of the REF module Selectable conversion clock source Single channel repeat single channel sequence and repeat sequence conversion modes Window comparator for low power monitoring of input signals Interrupt vector register for fast decoding of six ADC interrupts ADC10IFG0 ADC10...

Page 435: ...10INCHx A0 A1 A2 A3 A4 A5 A6 A7 A15 A14 A13 A12 TempSense Batt Monitor VEREF VEREF ADC10DIVx ADC10 PDIVx ADC10 SSELx ADC10BUSY ADC10SHP ADC10 MSC ADC10 SHTx SHI ADC10ISSH SAMPCON ADC10 MSC ADC10HIx ADC10LOx ADC10DF To Interrupt Logic 01 10 ADC10CLK Reference Buffer ADC10 SHSx www ti com ADC10_B Introduction A MODCLK is sourced from the MODOSC in the CS module See the CS chapter for more informatio...

Page 436: ...0_B source clock is selected using the ADC10SSELx bits Possible ADC10CLK sources are SMCLK MCLK ACLK and the MODCLK The input clock can be divided from 1 512 using both the ADC10DIVx bits and the ADC10PDIVx bits MODCLK generated internally in the CS is in the 5 MHz range but varies with individual devices supply voltage and temperature See the device specific data sheet for the MODOSC specificatio...

Page 437: ...e from the REF module must be enabled by software Its settling time is 30 µs See the REF module description for further information on the on chip reference The reference buffer of the ADC10_B also has selectable speed versus power settings When the maximum conversion rate is below 50 ksps setting ADC10SR 1 reduces the current consumption of the buffer by approximately 50 16 2 4 Auto Power Down Th...

Page 438: ... The SHI signal is used to trigger the sampling timer The ADC10SHTx bits in ADC10CTL0 control the interval of the sampling timer that defines the SAMPCON sample period tsample The sampling timer keeps SAMPCON high after synchronization with AD10CLK for a programmed interval tsample The total sampling time is tsample plus tsync see Figure 16 4 The ADC10SHTx bits select the sampling time in multiple...

Page 439: ...te 10 bit conversion Figure 16 5 Analog Input Equivalent Circuit The resistance of the source RS and RI affect tsample See the device specific datasheet for the tsample limits 16 2 6 Conversion Result The conversion result is accessible using the ADC10MEM0 register independently of the conversion mode selected by the user When a conversion result is written to ADC10MEM0 the ADC10IFG0 is set 16 2 7...

Page 440: ...le Conversion Mode A single channel selected by ADC10INCHx is sampled and converted once The ADC result is written to ADC10MEM0 Figure 16 6 shows the flow of the single channel single conversion mode When ADC10SC triggers a conversion successive conversions can be triggered by the ADC10SC bit When any other trigger source is used ADC10ENC must be toggled between each conversion Resetting the ADC10...

Page 441: ... A sequence of channels is sampled and converted once The sequence begins with the channel selected by the ADC10INCHx bits and decrements to channel A0 Each ADC result is written to ADC10MEM0 The sequence stops after conversion of channel A0 Figure 16 7 shows the sequence of channels mode When ADC10SC triggers a sequence successive sequences can be triggered by the ADC10SC bit When any other trigg...

Page 442: ...ter to the selected ADC10_A channel defined by All bit or registernames are marked with bold font signals are noted in normal font ADC10INCHx Sample Input Channel x ADC10_B Operation www ti com 16 2 7 3 Repeat Single Channel Mode A single channel selected by ADC10INCHx is sampled and converted continuously Each ADC result is written to ADC10MEM0 Figure 16 8 shows the repeat single channel mode Fig...

Page 443: ...put Channel x If x 0 then x x 1 else x ADC10INCHx SAMPCON If x 0 then x x 1 else x ADC10INCHx www ti com ADC10_B Operation 16 2 7 4 Repeat Sequence of Channels Mode A sequence of channels is sampled and converted repeatedly The sequence begins with the channel selected by ADC10INCHx and decrements to channel A0 Each ADC result is written to ADC10MEM0 The sequence ends after conversion of channel A...

Page 444: ...re unreliable 16 2 8 Window Comparator The window comparator allows to monitor analog signals without any CPU interaction The following list shows the available interrupt flags and the conditions when they are asserted The ADC10LO interrupt flag ADC10LOIFG is set if the current result of the ADC10_B conversion is below the low threshold defined in register ADC10LO The ADC10HI interrupt flag ADC10H...

Page 445: ... conversion mode selection The temperature sensor is located in the REF module of the device and must be activated by software Figure 16 10 shows the typical temperature sensor transfer function When using the temperature sensor the sample period must be greater than 30 µs The temperature sensor offset error can be large and may need to be calibrated for most applications see the device specific d...

Page 446: ... care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the ADC The connections shown in Figure 16 11 help to prevent this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design using s...

Page 447: ...pt source requested an interrupt The highest priority enabled ADC10_B interrupt generates a number in the ADC10IV register see register description This number can be evaluated or added to the program counter PC to automatically enter the appropriate software routine Disabled ADC10_B interrupts do not affect the ADC10IV value Read access of the ADC10IV register automatically resets the highest pen...

Page 448: ... Vector 6 ADC10_B window comparator high Interrupt JMP ADLO Vector 8 ADC10_B window comparator low Interrupt JMP ADIN Vector 10 ADC10_B window comparator in Interrupt Handler for ADC10IFG0 starts here No JMP required ADMEM MOV ADC10MEM0 xxx Move result flag is reset Other instruction needed RETI Return ADOV Handle ADCMEM0 overflow RETI Return ADTOV Handle Conv time overflow RETI Return ADHI Handle...

Page 449: ...n 16 3 3 06h ADC10LO ADC10_B Window Comparator Low Read write 0000h Section 16 3 9 Threshold register 08h ADC10HI ADC10_B Window Comparator High Read write FF03h Section 16 3 7 Threshold register 0Ah ADC10MCTL0 ADC10_B Memory Control register Read write 00h Section 16 3 6 12h ADC10MEM0 ADC10_B Conversion Memory register Read write undefined Section 16 3 4 1Ah ADC10IE ADC10_B Interrupt Enable regis...

Page 450: ...CLK cycles 0111b 192 ADC10CLK cycles 1000b 256 ADC10CLK cycles 1001b 384 ADC10CLK cycles 1010b 512 ADC10CLK cycles 1011b 768 ADC10CLK cycles 1100b 1024 ADC10CLK cycles 1101b 1024 ADC10CLK cycles 1110b 1024 ADC10CLK cycles 1111b 1024 ADC10CLK cycles 7 ADC10MSC RW 0h ADC10_B multiple sample and conversion Valid only for sequence or repeated modes Can be modified only when ADC10ENC 0 Resetting ADC10E...

Page 451: ...abled 0 ADC10SC RW 0h ADC10_B start conversion Software controlled sample and conversion start ADC10SC and ADC10ENC may be set together with one instruction ADC10SC is reset automatically 0b No sample and conversion start 1b Start sample and conversion 451 SLAU272C May 2011 Revised November 2013 ADC10_B Module Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 452: ...nd hold pulse mode select This bit selects the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly Can be modified only when ADC10ENC 0 Resetting ADC10ENC 0 by software and changing these fields immediately shows effect also when a conversion is active 0b SAMPCON signal is sourced from the sample input signal 1b SAMPCON signal is ...

Page 453: ...n sequence mode select Can be modified only when ADC10ENC 0 Resetting ADC10ENC 0 by software and changing these fields immediately shows effect also when a conversion is active 00b Single channel single conversion 01b Sequence of channels 10b Repeat single channel 11b Repeat sequence of channels 0 ADC10BUSY R 0h ADC10_B busy This bit indicates an active sample or conversion operation 0b No operati...

Page 454: ...is bit defines the conversion result resolution 0b 8 bit 10 clock cycle conversion time 1b 10 bit 12 clock cycle conversion time 3 ADC10DF RW 0h ADC10_B data read back format Data is always stored in the binary unsigned format 0b Binary unsigned Theoretically the analog input voltage V REF results in 0000h the analog input voltage V REF results in 03FFh 1b Signed binary 2s complement left aligned ...

Page 455: ...ADC10_B Conversion Memory Register 2s Complement Format Figure 16 16 ADC10MEM0 Register 15 14 13 12 11 10 9 8 Conversion_Results rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Conversion_Results rw rw r0 r0 r0 r0 r0 r0 Table 16 7 ADC10MEM0 Register Description Bit Field Type Reset Description 15 0 Conversion_Results RW undefined The 10 bit conversion results are left justified 2s complement format Bit 15...

Page 456: ... R AVCC and V R AVSS 001b V R VREF and V R AVSS 010b V R VEREF buffered and V R AVSS 011b V R VEREF and V R AVSS 100b V R AVCC and V R VEREF 101b V R VREF and V R VEREF 110b V R VEREF buffered and V R VEREF 111b V R VEREF and V R VEREF 3 0 ADC10INCHx RW 0h Input channel select Writing these bits select the channel for a single conversion or the highest channel for a sequence of conversions Reading...

Page 457: ...DC10DF 0 16 3 8 ADC10HI Register 2s Complement Format ADC10_B Window Comparator High Threshold Register 2s Complement Format Figure 16 19 ADC10HI Register 15 14 13 12 11 10 9 8 High_Threshold rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 7 6 5 4 3 2 1 0 High_Threshold rw 1 rw 1 r0 r0 r0 r0 r0 r0 Table 16 10 ADC10HI Register Description Bit Field Type Reset Description 15 0 High_Threshold RW 1FFh The 10 ...

Page 458: ...C10DF 0 16 3 10 ADC10LO Register 2s Complement Format ADC10_B Window Comparator Low Threshold Register 2s Complement Format Figure 16 21 ADC10LO Register 15 14 13 12 11 10 9 8 Low_Threshold rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 Low_Threshold rw 0 rw 0 r0 r0 r0 r0 r0 r0 Table 16 12 ADC10LO Register Description Bit Field Type Reset Description 15 0 Low_Threshold RW 200h The 10 bit ...

Page 459: ...flow interrupt enabled 3 ADC10HIIE RW 0h Interrupt enable for the above upper threshold interrupt of the window comparator 0b Above upper threshold interrupt disabled 1b Above upper threshold interrupt enabled 2 ADC10LOIE RW 0h Interrupt enable for the below lower threshold interrupt of the window comparator 0b Below lower threshold interrupt disabled 1b Below lower threshold interrupt enabled 1 A...

Page 460: ...he ADC10HIIFG is set when the result of the current ADC10_B conversion is greater than the upper threshold defined by the window comparator upper threshold register 0b No interrupt pending 1b Interrupt pending 2 ADC10LOIFG RW 0h The ADC10LOIFG is set when the result of the current ADC10_B conversion is below the lower threshold defined by the window comparator lower threshold register 0b No interr...

Page 461: ...clears all pending interrupt flags 00h No interrupt pending 02h Interrupt Source ADC10MEM0 overflow Interrupt Flag ADC10OVIFG Interrupt Priority Highest 04h Interrupt Source Conversion time overflow Interrupt Flag ADC10TOVIFG 06h Interrupt Source ADC10HI Interrupt flag Interrupt Flag ADC10HIIFG 08h Interrupt Source ADC10LO Interrupt flag Interrupt Flag ADC10LOIFG 0Ah Interrupt Source ADC10IN Inter...

Page 462: ...Comparator_D Comparator_D supports general comparator functionality for up to 16 channels Topic Page 17 1 Comparator_D Introduction 463 17 2 Comparator_D Operation 464 17 3 Comparator_D Registers 469 462 Comparator_D SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 463: ...al analog signals Features of Comparator_D include Inverting and noninverting terminal input multiplexer Software selectable RC filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator voltage hysteresis generator Reference voltage input from shared reference Interrupt driven meas...

Page 464: ...ping of both terminals of the internal multiplexer to the outside Internally the input switch is constructed as a T switch to suppress distortion in the signal path NOTE Comparator Input Connection When the comparator is on the input terminals should be connected to a signal power or ground Otherwise floating levels may cause unexpected interrupts and increased current consumption The CDEX bit con...

Page 465: ...t signals voltage level with 5 Tau it is charged to more than 99 and with 10 Tau the sampled voltage is sufficient for 12 bit accuracy 17 2 5 Output Filter The output of the comparator can be used with or without internal filtering When control bit CDF is set the output is filtered with an on chip RC filter The delay of the filter can be adjusted in four different steps All comparator outputs are ...

Page 466: ... either comparator input terminal The CDREF1x VREF1 and CDREF0x VREF0 bits control the output of the voltage generator The CDRSEL bit selects the comparator terminal to which VREF is applied If external signals are applied to both comparator input terminals the internal reference generator should be turned off to reduce current consumption The voltage reference generator can generate a fraction of...

Page 467: ...bits automatically disables the input buffer for that pin regardless of the state of the associated CDPDx bit Figure 17 5 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer 17 2 8 Comparator_D Interrupts One interrupt flag and one interrupt vector is associated with the Comparator_D The interrupt flag CDIFG is set on either the rising or falling edge of the comparator output s...

Page 468: ...inal of the capacitor The terminal is connected to a reference level for example 0 25 VCC The output filter should be used to minimize switching noise CDOUT is used to gate a timer capturing capacitor discharge time More than one resistive element can be measured Additional elements are connected to CD0 with available I O pins and switched to high impedance when not being measured The thermistor m...

Page 469: ...d write 0000h Section 17 3 1 02h CDCTL1 Comparator_D control register 1 Read write 0000h Section 17 3 2 04h CDCTL2 Comparator_D control register 2 Read write 0000h Section 17 3 3 06h CDCTL3 Comparator_D control register 3 Read write 0000h Section 17 3 4 0Ch CDINT Comparator_D interrupt register Read write 0000h Section 17 3 5 0Eh CDIV Comparator_D interrupt vector word Read 0000h Section 17 3 6 46...

Page 470: ...d 1b Selected analog input channel for V terminal is enabled 14 12 Reserved R 0h Reserved Always reads as 0 11 8 CDIMSEL RW 0h Channel input selected for the V terminal of the comparator if CDIMEN is set to 1 7 CDIPEN RW 0h Channel input enable for the V terminal of the comparator 0b Selected analog input channel for V terminal is disabled 1b Selected analog input channel for V terminal is enabled...

Page 471: ...ved R 0h Reserved Always reads as 0 7 6 CDFDLY RW 0h Filter delay The filter delay can be selected in 4 steps See the device specific data sheet for details 00b Typical filter delay of 0 5 µs 01b Typical filter delay of 0 9 µs 10b Typical filter delay of 1 6 µs 11b Typical filter delay of 3 µs 5 CDEX RW 0h Exchange This bit permutes the comparator 0 inputs and inverts the comparator 0 output 4 CDS...

Page 472: ...put 12 8 CDREF1 RW 0h Reference resistor tap 1 This register defines the tap of the resistor string while CDOUT 1 7 6 CDRS RW 0h Reference source This bit define if the reference voltage is derived from VCC or from the precise shared reference 00b No current is drawn by the reference circuitry 01b VCC applied to the resistor ladder 10b Shared reference voltage applied to the resistor ladder 11b Sh...

Page 473: ...0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 17 5 CDCTL3 Register Description Bit Field Type Reset Description 15 0 CDPDx RW 0h Port disable These bits individually disable the input buffer for the pins of the port associated with Comparator_D The bit CDPDx disabled the port of the comparator channel x 0b The input buffer is enabled 1b The input buffer is disabled 473 SLAU272C May 2011 Revised Novem...

Page 474: ...upt is disabled 1b Interrupt is enabled 8 CDIE RW 0h Comparator_D output interrupt enable 0b Interrupt is disabled 1b Interrupt is enabled 7 2 Reserved R 0h Reserved Always reads as 0 1 CDIIFG RW 0h Comparator_D output inverted interrupt flag The bit CDIES defines the transition of the output setting this bit 0b No interrupt pending 1b Output interrupt pending 0 CDIFG RW 0h Comparator_D output int...

Page 475: ...rd register The interrupt vector register reflects only interrupt flags whose interrupt enable bit are set Reading the CDIV register clears the pending interrupt flag with the highest priority 00h No interrupt pending 02h Interrupt Source CDOUT interrupt Interrupt Flag CDIFG Interrupt Priority Highest 04h Interrupt Source CDOUT interrupt inverted polarity Interrupt Flag CDIIFG Interrupt Priority L...

Page 476: ...his chapter discusses the operation of the asynchronous UART mode Topic Page 18 1 Enhanced Universal Serial Communication Interface A eUSCI_A Overview 477 18 2 eUSCI_A Introduction UART Mode 477 18 3 eUSCI_A Operation UART Mode 479 18 4 eUSCI_A UART Registers 494 476 Enhanced Universal Serial Communication Interface eUSCI UART Mode SLAU272C May 2011 Revised November 2013 Submit Documentation Feedb...

Page 477: ...te transmit and receive buffer registers LSB first or MSB first data transmit and receive Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes wake up from LPMx 5 is not supported Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression Sta...

Page 478: ...DA Decoder UCIRRXFE UCIRRXFLx 6 Transmit Buffer UCAxTXBUF Transmit State Machine UCTXADDR UCTXBRK Transmit Shift Register UCPEN UCPAR UCMSB UC7BIT UCIREN UCIRTXPLx 6 0 1 IrDA Encoder UCAxTXD Transmit Clock Receive Clock BRCLK UCMODEx 2 UCSPB UCRXEIE UCRXBRKIE Set UCRXIFG Set UCTXIFG Set RXIFG eUSCI_A Introduction UART Mode www ti com Figure 18 1 eUSCI_Ax Block Diagram UART Mode UCSYNC 0 478 Enhanc...

Page 479: ...r UCSWRST via software BIC B UCSWRST UCAxCTL1 5 Enable interrupts optional via UCRXIE or UCTXIE 18 3 2 Character Format The UART character format see Figure 18 2 consists of a start bit seven or eight data bits an even odd no parity bit an address bit address bit mode and one or two stop bits The UCMSB bit controls the direction of the transfer and selects LSB or MSB first LSB first is typically r...

Page 480: ...or address transmission in idle line multiprocessor format a precise idle period can be generated by the eUSCI_A to generate address character identifiers on UCAxTXD The double buffered UCTXADDR flag indicates if the next character loaded into UCAxTXBUF is preceded by an idle line of 11 bits UCTXADDR is automatically cleared when the start bit is generated 18 3 3 1 1 Transmitting an Idle Frame The...

Page 481: ...s and must reset UCDORM to continue receiving data If UCDORM remains set only address characters with address bit 1 are received The UCDORM bit is not modified by the eUSCI_A hardware automatically When UCDORM 0 all received characters set the receive interrupt flag UCRXIFG If UCDORM is cleared during the reception of a character the receive interrupt flag is set after the reception is completed F...

Page 482: ...ed to control data reception in this mode When UCDORM is set all characters are received but not transferred into the UCAxRXBUF and interrupts are not generated When a break synch field is detected the UCBRK flag is set The character following the break synch field is transferred into UCAxRXBUF and the UCRXIFG interrupt flag is set Any applicable error flag is also set If the UCBRKIE bit is set re...

Page 483: ...n is defined by UCIRTXPLx bits specifying the number of one half clock periods of the clock selected by UCIRTXCLK Figure 18 7 UART vs IrDA Data Format To set the pulse time of 3 16 bit period required by the IrDA standard the BITCLK16 clock is selected with UCIRTXCLK 1 and the pulse length is set to six one half clock cycles with UCIRTXPLx 6 1 5 When UCIRTXCLK 0 the pulse length tPULSE is based on...

Page 484: ...lation When a parity error is detected the UCPE bit is set Receive overrun UCOE An overrun error occurs when a character is loaded into UCAxRXBUF before the prior character has been read When an overrun occurs the UCOE bit is set Break condition UCBRK When not using automatic baud rate detection a break is detected when all data parity and stop bits are low When a break condition is detected the U...

Page 485: ...cific data sheet for parameters The deglitch time tt can be set to four different values using the UCGLITx bits Figure 18 8 Glitch Suppression eUSCI_A Receive Not Started When a glitch is longer than tt or a valid start bit occurs on UCAxRXD the eUSCI_A receive operation is started and a majority vote is taken see Figure 18 9 If the majority vote fails to detect a start bit the eUSCI_A halts chara...

Page 486: ...f the majority vote In low frequency mode the baud rate generator uses one prescaler and one modulator to generate bit clock timing This combination supports fractional divisors for baud rate generation In this mode the maximum eUSCI_A baud rate is one third the UART source clock frequency BRCLK Timing for each bit is shown in Figure 18 10 For each bit received a majority vote is taken to determin...

Page 487: ... the table indicates that the corresponding BITCLK16 period is one BRCLK period longer than the periods m 0 The modulation restarts with each new bit timing Modulation for BITCLK is based on the UCBRSx setting as previously described Table 18 3 BITCLK16 Modulation Pattern Number of BITCLK16 Clocks After Last Falling BITCLK Edge UCBRFx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 00h 0 0 0 0 0 0 0 0 0 0 0...

Page 488: ...x Settings for Fractional Portion of N fBRCLK Baudrate Fractional Portion of N UCBRSx 1 Fractional Portion of N UCBRSx 1 0 0000 0x00 0 5002 0xAA 0 0529 0x01 0 5715 0x6B 0 0715 0x02 0 6003 0xAD 0 0835 0x04 0 6254 0xB5 0 1001 0x08 0 6432 0xB6 0 1252 0x10 0 6667 0xD6 0 1430 0x20 0 7001 0xB7 0 1670 0x11 0 7147 0xBB 0 2147 0x21 0 7503 0xDD 0 2224 0x22 0 7861 0xED 0 2503 0x44 0 8004 0xEE 0 3000 0x25 0 8...

Page 489: ...the length of bit i Tbit TX i is based on the baud rate generator UCBRx UCBRFx and UCBRSx settings Where Sum of ones from the corresponding row in Table 18 3 mUCBRSx i Modulation of bit i of UCBRSx This results in an end of bit time tbit TX i equal to the sum of all previous and the current bit times To calculate bit error this time is compared to the ideal bit time tbit ideal TX i tbit ideal TX i...

Page 490: ...ronization error tSYNC This results in the following tbit RX i for the low frequency baud rate mode Where Tbit RX i 1 fBRCLK UCBRx mUCBRSx i mUCBRSx i Modulation of bit i of UCBRSx For the oversampling baud rate mode the sampling time tbit RX i of bit i is calculated by Where Sum of ones from columns 0 to 7 mUCBRSx i from the corresponding row in Table 18 3 mUCBRSx i Modulation of bit i of UCBRSx ...

Page 491: ... 93 14 92 4000000 9600 1 26 0 0xB6 0 08 0 16 0 28 0 2 4000000 19200 1 13 0 0x84 0 32 0 32 0 64 0 48 4000000 38400 1 6 8 0x20 0 48 0 64 1 04 1 04 4000000 57600 1 4 5 0x55 0 8 0 64 1 12 1 76 4000000 115200 1 2 2 0xBB 1 44 1 28 3 92 1 68 4000000 230400 0 17 0x4A 2 72 2 56 3 76 7 28 4194304 9600 1 27 4 0xFB 0 11 0 1 0 33 0 4194304 19200 1 13 10 0x55 0 21 0 21 0 55 0 33 4194304 38400 1 6 13 0x22 0 46 0...

Page 492: ... 57600 1 21 11 0x22 0 16 0 13 0 16 0 38 20000000 115200 1 10 13 0xAD 0 29 0 26 0 46 0 66 20000000 230400 1 5 6 0xEE 0 67 0 51 1 71 0 62 20000000 460800 1 2 11 0x92 1 38 0 99 1 84 2 8 18 3 14 Using the eUSCI_A Module in UART Mode With Low Power Modes The eUSCI_A module provides automatic clock activation for use with low power modes When the eUSCI_A clock source is inactive because the device is in...

Page 493: ...t flags are prioritized and combined to source a single interrupt vector The interrupt vector register UCAxIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the UCAxIV register that can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled interrupts do not affect the UCAxIV...

Page 494: ...18 4 4 0Ah UCAxSTATW eUSCI_Ax Status Read write Word 00h Section 18 4 5 0Ch UCAxRXBUF eUSCI_Ax Receive Buffer Read write Word 00h Section 18 4 6 0Eh UCAxTXBUF eUSCI_Ax Transmit Buffer Read write Word 00h Section 18 4 7 10h UCAxABCTL eUSCI_Ax Auto Baud Rate Control Read write Word 00h Section 18 4 8 12h UCAxIRCTL eUSCI_Ax IrDA Control Read write Word 0000h Section 18 4 9 12h UCAxIRTCTL eUSCI_Ax IrD...

Page 495: ...Character length Selects 7 bit or 8 bit character length 0b 8 bit data 1b 7 bit data 11 UCSPB RW 0h Stop bit select Number of stop bits 0b One stop bit 1b Two stop bits 10 9 UCMODEx RW 0h eUSCI_A mode The UCMODEx bits select the asynchronous mode when UCSYNC 0 00b UART mode 01b Idle line multiprocessor mode 10b Address bit multiprocessor mode 11b UART mode with automatic baud rate detection 8 UCSY...

Page 496: ...ten into UCAxTXBUF to generate the required break synch fields Otherwise 0h must be written into the transmit buffer 0b Next frame transmitted is not a break 1b Next frame transmitted is a break or a break synch 0 UCSWRST RW 1h Software reset enable 0b Disabled eUSCI_A reset released for operation 1b Enabled eUSCI_A logic held in reset state 18 4 2 UCAxCTLW1 Register eUSCI_Ax Control Word Register...

Page 497: ...5 4 3 2 1 0 UCBRFx Reserved UCOS16 rw 0 rw 0 rw 0 rw 0 r0 r0 r0 rw 0 Modify only when UCSWRST 1 Table 18 11 UCAxMCTLW Register Description Bit Field Type Reset Description 15 8 UCBRSx RW 0h Second modulation stage select These bits hold a free modulation pattern for BITCLK 7 4 UCBRFx RW 0h First modulation stage select These bits determine the modulation pattern for BITCLK16 when UCOS16 1 Ignored ...

Page 498: ...When UCPEN 0 UCPE is read as 0 UCPE is cleared when UCAxRXBUF is read 0b No error 1b Character received with parity error 3 UCBRK RW 0h Break detect flag UCBRK is cleared when UCAxRXBUF is read 0b No break condition 1b Break condition occurred 2 UCRXERR RW 0h Receive error flag This bit indicates a character was received with one or more errors When UCRXERR 1 on or more error flags UCFE UCPE or UC...

Page 499: ...and the MSB is always reset 18 4 7 UCAxTXBUF Register eUSCI_Ax Transmit Buffer Register Figure 18 18 UCAxTXBUF Register 15 14 13 12 11 10 9 8 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw Table 18 14 UCAxTXBUF Register Description Bit Field Type Reset Description 15 8 Reserved R 0h Reserved 7 0 UCTXBUFx RW 0h The transmit data buffer is user accessible a...

Page 500: ...times 10b 3 bit times 11b 4 bit times 3 UCSTOE RW 0h Synch field time out error 0b No error 1b Length of synch field exceeded measurable time 2 UCBTOE RW 0h Break time out error 0b No error 1b Length of break field exceeded 22 bit times 1 Reserved R 0h Reserved 0 UCABDEN RW 0h Automatic baud rate detect enable 0b Baud rate detection disabled Length of break and synch field is not measured 1b Baud ...

Page 501: ...eceive input UCAxRXD polarity 0b IrDA transceiver delivers a high pulse when a light pulse is seen 1b IrDA transceiver delivers a low pulse when a light pulse is seen 8 UCIRRXFE RW 0h IrDA receive filter enabled 0b Receive filter disabled 1b Receive filter enabled 7 2 UCIRTXPLx RW 0h Transmit pulse length Pulse length t PULSE UCIRTXPLx 1 2 f IRTXCLK 1 UCIRTXCLK RW 0h IrDA transmit pulse clock sele...

Page 502: ...served R 0h Reserved 3 UCTXCPTIE RW 0h Transmit complete interrupt enable 0b Interrupt disabled 1b Interrupt enabled 2 UCSTTIE RW 0h Start bit interrupt enable 0b Interrupt disabled 1b Interrupt enabled 1 UCTXIE RW 0h Transmit interrupt enable 0b Interrupt disabled 1b Interrupt enabled 0 UCRXIE RW 0h Receive interrupt enable 0b Interrupt disabled 1b Interrupt enabled 502 Enhanced Universal Serial ...

Page 503: ...shift register got shifted out and UCAxTXBUF is empty 0b No interrupt pending 1b Interrupt pending 2 UCSTTIFG RW 0h Start bit interrupt flag UCSTTIFG is set after a Start bit was received 0b No interrupt pending 1b Interrupt pending 1 UCTXIFG RW 1h Transmit interrupt flag UCTXIFG is set when UCAxTXBUF empty 0b No interrupt pending 1b Interrupt pending 0 UCRXIFG RW 0h Receive interrupt flag UCRXIFG...

Page 504: ...or value 00h No interrupt pending 02h Interrupt Source Receive buffer full Interrupt Flag UCRXIFG Interrupt Priority Highest 04h Interrupt Source Transmit buffer empty Interrupt Flag UCTXIFG 06h Interrupt Source Start bit received Interrupt Flag UCSTTIFG 08h Interrupt Source Transmit complete Interrupt Flag UCTXCPTIFG Interrupt Priority Lowest 504 Enhanced Universal Serial Communication Interface ...

Page 505: ...s the operation of the synchronous peripheral interface SPI mode Topic Page 19 1 Enhanced Universal Serial Communication Interfaces eUSCI_A eUSCI_B Overview 506 19 2 eUSCI Introduction SPI Mode 506 19 3 eUSCI Operation SPI Mode 508 19 4 eUSCI_A SPI Registers 514 19 5 eUSCI_B SPI Registers 524 505 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eUSCI SPI Mo...

Page 506: ...its SPI mode features include 7 bit or 8 bit data length LSB first or MSB first data transmit and receive 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer registers Continuous transmit and receive operation Selectable clock polarity and phase control Programmable clock frequency in master mode Independent inte...

Page 507: ...er UCMSB UC7BIT BRCLK Set UCxRXIFG Set UCxTXIFG 0 1 UCLISTEN Clock Direction Phase and Polarity UCCKPH UCCKPL UCxSIMO UCxCLK Set UCOE Transmit Enable Control UCSTEM UCxSTE Set UCFE 2 UCMODEx www ti com eUSCI Introduction SPI Mode Figure 19 1 eUSCI Block Diagram SPI Mode 507 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eUSCI SPI Mode Submit Documentation...

Page 508: ...ter Active State 0 Inactive Active 01 High 1 Active Inactive 0 Active Inactive 10 Low 1 Inactive Active 19 3 1 eUSCI Initialization and Reset The eUSCI is reset by a PUC or by the UCSWRST bit After a PUC the UCSWRST bit is automatically set keeping the eUSCI in a reset condition When set the UCSWRST bit resets the UCRXIE UCTXIE UCRXIFG UCOE and UCFE bits and sets the UCTXIFG flag Clearing UCSWRST ...

Page 509: ...ft register when the TX shift register is empty initiating data transfer on UCxSIMO starting with either the MSB or LSB depending on the UCMSB setting Data on UCxSOMI is shifted into the receive shift register on the opposite clock edge When the character is received the receive data is moved from the receive RX shift register to the received data buffer UCxRXBUF and the receive interrupt flag UCR...

Page 510: ... If UCSTEM 1 in 4 pin master mode UCxSTE is a digital output In this mode the slave enable signal for a single slave is automatically generated on UCxSTE The corresponding behavior can be seen in Figure 19 4 If multiple slaves are desired this feature is not applicable and the software needs to use general purpose I O pins instead to generate STE signals for each slave individually 19 3 4 Slave Mo...

Page 511: ...ons operate concurrently 19 3 6 Serial Clock Control UCxCLK is provided by the master on the SPI bus When UCMST 1 the bit clock is provided by the eUSCI bit clock generator on the UCxCLK pin The clock used to generate the bit clock is selected with the UCSSELx bits When UCMST 0 the eUSCI clock is provided on the UCxCLK pin by the master the bit clock generator is not used and the UCSSELx bits are ...

Page 512: ...ake up the CPU from any low power mode When receiving multiple bytes as a slave in LPM4 the wakeup time of the CPU needs to be considered If the wake up time of the CPU is for example 150 µs see device specific data sheet it needs to be ensured that the CPU serves the TXIFG of the first received byte before the second byte is completely received by the eUSCI_A or eUSCI_B Otherwise an overrun error...

Page 513: ...ally enter the appropriate software routine Disabled interrupts do not affect the UCxIV value Any access read or write of the UCxIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt 19 3 8 3 1 UCxIV Software Example The following software example shows the recommended us...

Page 514: ...00h Section 19 4 2 06h UCAxBR0 eUSCI_Ax Bit Rate Control 0 Read write Byte 00h 07h UCAxBR1 eUSCI_Ax Bit Rate Control 1 Read write Byte 00h 0Ah UCAxSTATW eUSCI_Ax Status Read write Word 00h Section 19 4 3 0Ch UCAxRXBUF eUSCI_Ax Receive Buffer Read write Word 00h Section 19 4 4 0Eh UCAxTXBUF eUSCI_Ax Transmit Buffer Read write Word 00h Section 19 4 5 1Ah UCAxIE eUSCI_Ax Interrupt Enable Read write W...

Page 515: ...cts 7 bit or 8 bit character length 0b 8 bit data 1b 7 bit data 11 UCMST RW 0h Master mode select 0b Slave mode 1b Master mode 10 9 UCMODEx RW 0h eUSCI mode The UCMODEx bits select the synchronous mode when UCSYNC 1 00b 3 pin SPI 01b 4 pin SPI with UCxSTE active high Slave enabled when UCxSTE 1 10b 4 pin SPI with UCxSTE active low Slave enabled when UCxSTE 0 11b Reserved 8 UCSYNC RW 0h Synchronous...

Page 516: ... 0 UCSWRST RW 1h Software reset enable 0b Disabled eUSCI reset released for operation 1b Enabled eUSCI logic held in reset state 516 Enhanced Universal Serial Communication Interface eUSCI SPI Mode SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 517: ...0 UCBRx rw rw rw rw rw rw rw rw Modify only when UCSWRST 1 Table 19 4 UCAxBRW Register Description Bit Field Type Reset Description 15 0 UCBRx RW 0h Bit clock prescaler setting fBitClock fBRCLK UCBRx 1 517 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eUSCI SPI Mode Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 518: ...tes a bus conflict in 4 wire master mode UCFE is not used in 3 wire master or any slave mode 0b No error 1b Bus conflict occurred 5 UCOE RW 0h Overrun error flag This bit is set when a character is transferred into UCxRXBUF before the previous character was read UCOE is cleared automatically when UCxRXBUF is read and must not be cleared by software Otherwise it does not function correctly 0b No er...

Page 519: ...scription 15 8 Reserved R 0h Reserved 7 0 UCRXBUFx R 0h The receive data buffer is user accessible and contains the last received character from the receive shift register Reading UCxRXBUF resets the receive error bits and UCRXIFG In 7 bit data mode UCxRXBUF is LSB justified and the MSB is always reset 519 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eU...

Page 520: ... Description 15 8 Reserved R 0h Reserved 7 0 UCTXBUFx RW 0h The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted Writing to the transmit data buffer clears UCTXIFG The MSB of UCxTXBUF is not used for 7 bit data and is reset 520 Enhanced Universal Serial Communication Interface eUSCI SPI Mode SLAU272C May 2011 Revised No...

Page 521: ...le 19 8 UCAxIE Register Description Bit Field Type Reset Description 15 2 Reserved R 0h Reserved 1 UCTXIE RW 0h Transmit interrupt enable 0b Interrupt disabled 1b Interrupt enabled 0 UCRXIE RW 0h Receive interrupt enable 0b Interrupt disabled 1b Interrupt enabled 521 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eUSCI SPI Mode Submit Documentation Feedba...

Page 522: ... Reset Description 15 2 Reserved R 0h Reserved 1 UCTXIFG RW 1h Transmit interrupt flag UCTXIFG is set when UCxxTXBUF empty 0b No interrupt pending 1b Interrupt pending 0 UCRXIFG RW 0h Receive interrupt flag UCRXIFG is set when UCxxRXBUF has received a complete character 0b No interrupt pending 1b Interrupt pending 522 Enhanced Universal Serial Communication Interface eUSCI SPI Mode SLAU272C May 20...

Page 523: ...Field Type Reset Description 15 0 UCIVx R 0h eUSCI interrupt vector value 000h No interrupt pending 002h Interrupt Source Data received Interrupt Flag UCRXIFG Interrupt Priority Highest 004h Interrupt Source Transmit buffer empty Interrupt Flag UCTXIFG Interrupt Priority Lowest 523 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eUSCI SPI Mode Submit Docum...

Page 524: ...000h Section 19 5 2 06h UCBxBR0 eUSCI_Bx Bit Rate Control 0 Read write Byte 00h 07h UCBxBR1 eUSCI_Bx Bit Rate Control 1 Read write Byte 00h 08h UCBxSTATW eUSCI_Bx Status Read write Word 00h Section 19 5 3 0Ch UCBxRXBUF eUSCI_Bx Receive Buffer Read write Word 00h Section 19 5 4 0Eh UCBxTXBUF eUSCI_Bx Transmit Buffer Read write Word 00h Section 19 5 5 2Ah UCBxIE eUSCI_Bx Interrupt Enable Read write ...

Page 525: ...cts 7 bit or 8 bit character length 0b 8 bit data 1b 7 bit data 11 UCMST RW 0h Master mode select 0b Slave mode 1b Master mode 10 9 UCMODEx RW 0h eUSCI mode The UCMODEx bits select the synchronous mode when UCSYNC 1 00b 3 pin SPI 01b 4 pin SPI with UCxSTE active high Slave enabled when UCxSTE 1 10b 4 pin SPI with UCxSTE active low Slave enabled when UCxSTE 0 11b I2C mode 8 UCSYNC RW 1h Synchronous...

Page 526: ...n 0 UCSWRST RW 1h Software reset enable 0b Disabled eUSCI reset released for operation 1b Enabled eUSCI logic held in reset state 526 Enhanced Universal Serial Communication Interface eUSCI SPI Mode SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 527: ...nable The UCLISTEN bit selects loopback mode 0b Disabled 1b Enabled The transmitter output is internally fed back to the receiver 6 UCFE RW 0h Framing error flag This bit indicates a bus conflict in 4 wire master mode UCFE is not used in 3 wire master or any slave mode 0b No error 1b Bus conflict occurred 5 UCOE RW 0h Overrun error flag This bit is set when a character is transferred into UCxRXBUF...

Page 528: ...the MSB is always reset 19 5 5 UCBxTXBUF Register eUSCI_Bx Transmit Buffer Register Figure 19 17 UCBxTXBUF Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw Table 19 16 UCBxTXBUF Register Description Bit Field Type Reset Description 15 8 Reserved R 0h Reserved 7 0 UCTXBUFx RW 0h The transmit data buffer is user accessible and holds the...

Page 529: ...Bx Interrupt Flag Register Figure 19 19 UCBxIFG Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved UCTXIFG UCRXIFG r 0 r 0 r 0 r 0 r 0 r 0 rw 1 rw 0 Table 19 18 UCBxIFG Register Description Bit Field Type Reset Description 15 2 Reserved R 0h Reserved 1 UCTXIFG RW 1h Transmit interrupt flag UCTXIFG is set when UCxxTXBUF empty 0b No interrupt pending 1b Interrup...

Page 530: ...eld Type Reset Description 15 0 UCIVx R 0h eUSCI interrupt vector value 0000h No interrupt pending 0002h Interrupt Source Data received Interrupt Flag UCRXIFG Interrupt Priority Highest 0004h Interrupt Source Transmit buffer empty Interrupt Flag UCTXIFG Interrupt Priority Lowest 530 Enhanced Universal Serial Communication Interface eUSCI SPI Mode SLAU272C May 2011 Revised November 2013 Submit Docu...

Page 531: ...odule This chapter discusses the operation of the I2 C mode Topic Page 20 1 Enhanced Universal Serial Communication Interface B eUSCI_B Overview 532 20 2 eUSCI_B Introduction I2 C Mode 532 20 3 eUSCI_B Operation I2 C Mode 533 20 4 eUSCI_B I2C Registers 553 531 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eUSCI I2 C Mode Submit Documentation Feedback Cop...

Page 532: ...rface The eUSCI_B I2 C mode features include 7 bit and 10 bit device addressing modes General call START RESTART STOP Multi master transmitter or receiver mode Slave receiver or transmitter mode Standard mode up to 100 kbps and fast mode up to 400 kbps support Programmable UCxCLK frequency in master mode Designed for low power 8 bit byte counter with interrupt capability and automatic STOP asserti...

Page 533: ...Mode 20 3 eUSCI_B Operation I2 C Mode The I2 C mode supports any slave or master I2 C compatible device Figure 20 2 shows an example of an I2 C bus Each I2 C device is recognized by a unique address and can operate as either a transmitter or a receiver A device connected to the I2 C bus can be considered as the master or the slave when performing data transfers A master initiates a data transfer a...

Page 534: ...4 are cleared Registers UCBxIE and UCBxIFG are cleared All other bits and registers remain unchanged NOTE Initializing or re configuring the eUSCI_B module The recommended eUSCI_B initialization reconfiguration process is 1 Set UCSWRST BIS B UCSWRST UCxCTL1 2 Initialize all eUSCI_B registers with UCSWRST 1 including UCxCTL1 3 Configure ports 4 Clear UCSWRST via software BIC B UCSWRST UCxCTL1 5 Ena...

Page 535: ...ed Figure 20 4 Bit Transfer on I2 C Bus 20 3 3 I2 C Addressing Modes The I2 C mode supports 7 bit and 10 bit addressing modes 20 3 3 1 7 Bit Addressing In the 7 bit addressing format see Figure 20 5 the first byte is the 7 bit slave address and the R W bit The ACK bit is sent from the receiver after each byte Figure 20 5 I2 C Module 7 Bit Addressing Format 20 3 3 2 10 Bit Addressing In the 10 bit ...

Page 536: ...With 7 Bit Address UCBxCTL1 UCSWRST put eUSCI_B in reset state UCBxCTLW0 UCMODE_3 UCMST I2C master mode UCBxBRW 0x0008 baudrate SMCLK 8 UCBxCTLW1 UCASTP_2 autom STOP assertion UCBxTBCNT 0x07 TX 7 bytes of data UCBxI2CSA 0x0012 address slave is 12hex P2SEL 0x03 configure I2C pins device specific UCBxCTL1 UCSWRST eUSCI_B in operational state UCBxIE UCTXIE enable TX interrupt GIE general interrupt en...

Page 537: ...sed The RX interrupt service routine is called for every byte received by a master device The TX interrupt service routine is executed each time the master requests a byte The recommended structure of the interrupt service routine can be found in Example 20 3 20 3 5 I2 C Module Operating Modes In I2 C mode the eUSCI_B module can operate in master transmitter master receiver slave transmitter or sl...

Page 538: ... transmitted by the master is identical to its own address with a set R W bit The slave transmitter shifts the serial data out on SDA with the clock pulses that are generated by the master device The slave device does not generate the clock but it does hold SCL low while intervention of the CPU is required after a byte has been transmitted If the master requests data from the slave the eUSCI_B mod...

Page 539: ...ived If the slave receives data from the master the eUSCI_B module is automatically configured as a receiver and UCTR is cleared After the first data byte is received the receive interrupt flag UCRXIFG0 is set The eUSCI_B module automatically acknowledges the received data and can receive the next data byte If the previous data was not read from the receive buffer UCBxRXBUF at the end of a recepti...

Page 540: ...ne returns to its address reception state Figure 20 10 shows the I2 C slave receiver operation Figure 20 10 I2 C Slave Receiver Mode 20 3 5 1 3 I2 C Slave 10 Bit Addressing Mode The 10 bit addressing mode is selected when UCA10 1 and is as shown in Figure 20 11 In 10 bit addressing mode the slave is in receive mode after the full address is received The eUSCI_B module indicates this by setting the...

Page 541: ... master system UCMM must be set and its own address must be programmed into the UCBxI2COA0 register Support for multiple slave addresses is explained in Section 20 3 9 When UCA10 0 7 bit addressing is selected When UCA10 1 10 bit addressing is selected The UCGCEN bit selects if the eUSCI_B module responds to a general call NOTE Addresses and multi master systems In master mode with own address det...

Page 542: ... module waits for data to be written into UCBxTXBUF a STOP condition is generated even if no data was transmitted to the slave In this case the UCSTPIFG is set When transmitting a single byte of data the UCTXSTP bit must be set while the byte is being transmitted or any time after transmission begins without writing new data into UCBxTXBUF Otherwise only the address is transmitted When the data is...

Page 543: ... continues A UCALIFG 1 UCMST 0 UCTR 0 Receiver UCSTTIFG 1 UCGC 1 if general call USCI continues as Slave Receiver Not acknowledge received after a data byte UCTXSTT 0 UCTXSTP 0 UCTXSTP 0 UCALIFG 1 UCMST 0 Bus stalled SCL held low until data available Write data to UCBxTXBUF 1 UCTR 1 Transmitter 2 UCTXSTT 1 UCTXIFG 1 UCBxTXBUF discarded UCTXSTT 0 UCNACKIFG 1 UCBxTXBUF discarded UCTXIFG 1 UCBxTXBUF ...

Page 544: ... not acknowledge interrupt flag UCNACKIFG is set The master must react with either a STOP condition or a repeated START condition A STOP condition is either generated by the automatic STOP generation or by setting the UCTXSTP bit The next byte received from the slave is followed by a NACK and a STOP condition This NACK occurs immediately if the eUSCI_B module is currently waiting for UCBxRXBUF to ...

Page 545: ...TR 0 Receiver 2 UCTXSTT 1 Arbitration lost in slave address or data byte A Other master continues UCALIFG 1 UCMST 0 Arbitration lost and addressed as slave Other master continues A UCALIFG 1 UCMST 0 UCTR 1 Transmitter UCSTTIFG 1 UCTXIFG 1 USCI continues as Slave Transmitter A A A UCTXSTT 0 UCTXSTP 0 UCTXIFG 1 UCALIFG 1 UCMST 0 UCTXSTP 1 UCTXSTP 0 www ti com eUSCI_B Operation I2 C Mode Figure 20 13...

Page 546: ...transmitters The first master transmitter that generates a logic high is overruled by the opposing master generating a logic low The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value The master transmitter that lost arbitration switches to the slave receiver mode and sets the arbitration lost flag UCALIFG If two or more devices se...

Page 547: ...en by fBitClock fBRCLK UCBRx The minimum high and low periods of the generated SCL are tLOW MIN tHIGH MIN UCBRx 2 fBRCLK when UCBRx is even tLOW MIN tHIGH MIN UCBRx 1 2 fBRCLK when UCBRx is odd The eUSCI_B clock source frequency and the prescaler setting UCBRx must to be chosen such that the minimum low and high period times of the I2 C specification are met During the arbitration procedure the cl...

Page 548: ...It is possible to detect the situation when a clock is stretched by a master or slave for a too long time The user can then for example reset the eUSCI_B module by using the UCSWRST bit The clock low timeout feature is enabled using the UCCLTO bits It is possible to select one of three predefined times for the clock low timeout If the clock has been low longer than the time defined with the UCCLTO...

Page 549: ... to the received address is updated The state change interrupt flags are independent of the address comparison result They are updated according to the bus condition 20 3 9 2 Address Mask Register The address mask register can be used when the eUSCI_B is configured in slave or in multiple master mode To activate this feature at least one bit of the address mask in register UCBxADDMASK must be clea...

Page 550: ...mode with automatic STOP generation UCASTPx 10 the UCTXIFG0 is set as many times as defined in UCBxTBCNT An interrupt request is generated if UCTXIEx and GIE are also set UCTXIFGx is automatically reset if a write to UCBxTXBUF occurs or if the UCALIFG is cleared UCTXIFGx is set when Master mode UCTXSTT was set by the user Slave mode own address was received UCETXINT 0 or START was received UCETXIN...

Page 551: ...is flag is set when the I2 C module detects a START condition together with its own address 1 UCSTTIFG is used in slave mode only UCSTPIFG STOP condition detected interrupt This flag is set when the I2 C module detects a STOP condition on the bus UCSTPIFG is used in slave and master mode 1 The address evaluation includes the address mask register if it is used 20 3 11 5 UCBxIV Interrupt Vector Gen...

Page 552: ... RXIFG3 break case 0x0c Vector 12 TXIFG3 break case 0x0e Vector 14 RXIFG2 break case 0x10 Vector 16 TXIFG2 break case 0x12 Vector 18 RXIFG1 break case 0x14 Vector 20 TXIFG1 break case 0x16 Vector 22 RXIFG0 break case 0x18 Vector 24 TXIFG0 break case 0x1a Vector 26 BCNTIFG break case 0x1c Vector 28 clock low timeout break case 0x1e Vector 30 9th bit break default break 552 SLAU272C May 2011 Revised...

Page 553: ...BxTBCNT Read Write Word 00h Section 20 4 5 Register 0Ch UCBxRXBUF eUSCI_Bx Receive Buffer Read write Word 00h Section 20 4 6 0Eh UCBxTXBUF eUSCI_Bx Transmit Buffer Read write Word 00h Section 20 4 7 14h UCBxI2COA0 eUSCI_Bx I2C Own Address 0 Read write Word 0000h Section 20 4 8 16h UCBxI2COA1 eUSCI_Bx I2C Own Address 1 Read write Word 0000h Section 20 4 9 18h UCBxI2COA2 eUSCI_Bx I2C Own Address 2 R...

Page 554: ...environment UCMM 1 the UCMST bit is automatically cleared and the module acts as slave 0b Slave mode 1b Master mode 10 9 UCMODEx RW 0h eUSCI_B mode The UCMODEx bits select the synchronous mode when UCSYNC 1 Modify only when UCSWRST 1 00b 3 pin SPI 01b 4 pin SPI master or slave enabled if STE 1 10b 4 pin SPI master or slave enabled if STE 0 11b I2C mode 8 UCSYNC RW 1h Synchronous mode enable For eU...

Page 555: ...care if automatic UCASTPx is different from 01 or 10 0b No STOP generated 1b Generate STOP 1 UCTXSTT RW 0h Transmit START condition in master mode Ignored in slave mode In master receiver mode a repeated START condition is preceded by a NACK UCTXSTT is automatically cleared after START condition and address information is transmitted Ignored in slave mode 0b Do not generate START condition 1b Gene...

Page 556: ...ecification and should only be used for slaves which automatically release the SDA after a fixed packet length Modify only when UCSWRST 1 0b Send a non acknowledge before the STOP condition as a master receiver conform to I2C standard 1b All bytes are acknowledged by the eUSCI_B when configured as master receiver 4 UCSWACK RW 0h Using this bit it is possible to select whether the eUSCI_B module tr...

Page 557: ...eld Type Reset Description 1 0 UCGLITx RW 0h Deglitch time 00b 50 ns 01b 25 ns 10b 12 5 ns 11b 6 25 ns 557 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eUSCI I2 C Mode Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 558: ...Field Type Reset Description 15 8 UCBCNTx R 0h Hardware byte counter value Reading this register returns the number of bytes received or transmitted on the I2C Bus since the last START or RESTART There is no synchronization of this register done When reading UCBxBCNT during the first bit position a faulty readback can occur 7 Reserved R 0h Reserved 6 UCSCLLOW R 0h SCL low 0b SCL is not held low 1b...

Page 559: ...r Description Bit Field Type Reset Description 15 8 Reserved R 0h Reserved 7 0 UCTBCNTx RW 0h The byte counter threshold value is used to set the number of I2C data bytes after which the automatic STOP or the UCSTPIFG should occur This value is evaluated only if UCASTPx is different from 00 Modify only when UCSWRST 1 559 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communicati...

Page 560: ...ags 20 4 7 UCBxTXBUF eUSCI_Bx Transmit Buffer Register Figure 20 23 UCBxTXBUF Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw Table 20 10 UCBxTXBUF Register Description Bit Field Type Reset Description 15 8 Reserved R 0h Reserved 7 0 UCTXBUFx RW 0h The transmit data buffer is user accessible and holds the data waiting to be moved int...

Page 561: ...ed R 0h Reserved 10 UCOAEN RW 0h Own Address enable register With this register it can be selected if the I2C slave address related to this register UCBxI2COA0 is evaluated or not Modify only when UCSWRST 1 0b The slave address defined in I2COA0 is disabled 1b The slave address defined in I2COA0 is enabled 9 0 I2COAx RW 0h I2C own address The I2COA0 bits contain the local address of the eUSCIx_B I...

Page 562: ...y only when UCSWRST 1 20 4 10 UCBxI2COA2 Register eUSCI_Bx I2C Own Address 2 Register Figure 20 26 UCBxI2COA2 Register 15 14 13 12 11 10 9 8 Reserved UCOAEN I2COA2 rw 0 r0 r0 r0 r0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 I2COA2 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modify only when UCSWRST 1 Table 20 13 UCBxI2COA2 Register Description Bit Field Type Reset Description 15 11 Reserved R 0h Reserved 10 UCOAE...

Page 563: ...l address of the eUSCIx_B I2C controller The address is right justified In 7 bit addressing mode bit 6 is the MSB and bits 9 7 are ignored In 10 bit addressing mode bit 9 is the MSB Modify only when UCSWRST 1 20 4 12 UCBxADDRX Register eUSCI_Bx I2C Received Address Register Figure 20 28 UCBxADDRX Register 15 14 13 12 11 10 9 8 Reserved ADDRXx r 0 r0 r0 r0 r0 r0 r 0 r 0 7 6 5 4 3 2 1 0 ADDRXx r 0 r...

Page 564: ...mask feature is deactivated Modify only when UCSWRST 1 20 4 14 UCBxI2CSA Register eUSCI_Bx I2C Slave Address Register Figure 20 30 UCBxI2CSA Register 15 14 13 12 11 10 9 8 Reserved I2CSAx r 0 r0 r0 r0 r0 r0 rw 0 rw 0 7 6 5 4 3 2 1 0 I2CSAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 20 17 UCBxI2CSA Register Description Bit Field Type Reset Description 15 10 Reserved R 0h Reserved 9 0 I2CSAx RW 0...

Page 565: ...errupt enable 2 0b Interrupt disabled 1b Interrupt enabled 10 UCRXIE2 RW 0h Receive interrupt enable 2 0b Interrupt disabled 1b Interrupt enabled 9 UCTXIE1 RW 0h Transmit interrupt enable 1 0b Interrupt disabled 1b Interrupt enabled 8 UCRXIE1 RW 0h Receive interrupt enable 1 0b Interrupt disabled 1b Interrupt enabled 7 UCCLTOIE RW 0h Clock low timeout interrupt enable 0b Interrupt disabled 1b Inte...

Page 566: ...d 1b Interrupt enabled 1 UCTXIE0 RW 0h Transmit interrupt enable 0 0b Interrupt disabled 1b Interrupt enabled 0 UCRXIE0 RW 0h Receive interrupt enable 0 0b Interrupt disabled 1b Interrupt enabled 566 SLAU272C May 2011 Revised November 2013 Enhanced Universal Serial Communication Interface eUSCI I2 C Mode Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 567: ...ty in slave mode if the slave address defined in UCBxI2COA2 was on the bus in the same frame 0b No interrupt pending 1b Interrupt pending 10 UCRXIFG2 RW 0h Receive interrupt flag 2 UCRXIFG2 is set when UCBxRXBUF has received a complete byte in slave mode and if the slave address defined in UCBxI2COA2 was on the bus in the same frame 0b No interrupt pending 1b Interrupt pending 9 UCTXIFG1 RW 0h eUS...

Page 568: ...nding 1b Interrupt pending 1 UCTXIFG0 RW 0h eUSCI_B transmit interrupt flag 0 UCTXIFG0 is set when UCBxTXBUF is empty in master mode or in slave mode if the slave address defined in UCBxI2COA0 was on the bus in the same frame 0b No interrupt pending 1b Interrupt pending 0 UCRXIFG0 RW 0h eUSCI_B receive interrupt flag 0 UCRXIFG0 is set when UCBxRXBUF has received a complete character in master mode...

Page 569: ...n received Interrupt Flag UCSTPIFG 0Ah Interrupt Source Slave 3 Data received Interrupt Flag UCRXIFG3 0Ch Interrupt Source Slave 3 Transmit buffer empty Interrupt Flag UCTXIFG3 0Eh Interrupt Source Slave 2 Data received Interrupt Flag UCRXIFG2 10h Interrupt Source Slave 2 Transmit buffer empty Interrupt Flag UCTXIFG2 12h Interrupt Source Slave 1 Data received Interrupt Flag UCRXIFG1 14h Interrupt ...

Page 570: ...ion module EEM that is implemented in all devices Topic Page 21 1 Embedded Emulation Module EEM Introduction 571 21 2 EEM Building Blocks 573 21 3 EEM Configurations 574 570 Embedded Emulation Module EEM SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 571: ...er access triggers can be combined to form up to ten device dependent complex triggers or breakpoints Up to two device dependent cycle counters Trigger sequencing device dependent Storage of internal bus and control signals using an integrated trace buffer device dependent Clock control for timers communication peripherals and other modules on a global device level or on a per module basis during ...

Page 572: ... 3 4 5 6 7 8 9 Start Stop Cycle Counter Start Stop State Storage OR OR OR Embedded Emulation Module EEM Introduction www ti com Figure 21 1 Large Implementation of EEM 572 Embedded Emulation Module EEM SLAU272C May 2011 Revised November 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 573: ...The comparison can also be limited to certain bits with the use of a bit mask Both types of triggers can be combined to form more complex triggers For example a complex trigger can signal when a particular value is written into a user specified address 21 2 2 Trigger Sequencer The trigger sequencer allows the definition of a certain sequence of trigger signals before an event is accepted for a bre...

Page 574: ...User s Guide SLAU138 Code Composer Studio v4 2 for MSP430 User s Guide SLAU157 Table 21 1 EEM Configurations Feature XS S M L Memory bus triggers 2 3 5 8 only Memory bus trigger mask for 1 Low byte 1 Low byte 1 Low byte All 16 or 20 bits 2 High byte 2 High byte 2 High byte 3 Four upper addr bits 3 Four upper addr bits 3 Four upper addr bits CPU register write triggers 0 1 1 2 Combination triggers ...

Page 575: ...XIE to figure names were missing no change to register operation Table 19 13 Added fBitClock equation Figure 19 18 Added UCTXIE and UCRXIE to figure names were missing no change to register operation Figure 20 1 Changed MODOSC to MODCLK in figure Section 20 3 8 Changed The byte counter is also incremented at the second byte position to second bit position Section 20 3 9 2 Added to the description ...

Page 576: ...nformation regarding JTAG pins Section 1 13 Added notes regarding JTAG unlock via the tool chain Section 1 13 Added note regarding customer returns of devices on which JTAG is protected Section 1 14 Updated CRC generation method Section 1 14 Removed peripheral descriptor from TLV information Section 1 16 Removed SNMI MPU violations Section 2 3 1 Clarified PMM password register description Table 3 ...

Page 577: ...garding support of calendar mode only Chapter 13 Removed information regarding backup operation because it is not supported in the FR57xx family Section 14 2 4 Clarified references to radix rather than decimal point and decimal number representations Section 16 2 3 Added information regarding the internal AVCC can also be used as the reference Chapter 18 Changed chapter titles to include Enhanced ...

Page 578: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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