Audio output jack
MSP430FG4618/F2013 Experimenter's Board
RF Daughter Card Connect
Isolated RS232 Communication
Breadboard
Sallen-Key 2nd Order OA1 Active LPF
(For opt. F2013 programming)
0-00
SoftBaugh SBLCDA4
(A4/OA1I0)
(A3/OA1O)
(A7/DAC1)
(A0/OA0I0)
(A5/OA2O)
(A1/OA0O)
(A2/OA0I1)
(Mic Supply)
MSP430FG4618 Pin Access
Power Supply Configuration
(Output
Attn.)
VCC_1: FG4618 Supply Config
Pos 1-2: FET Powered
VCC_2: F2013 Supply Config
Pos 2-3: Battery Powered
Buzzer
Mute
Mic Input Circuitry and
1st Order OA0 Active HPF
MSP-EXP430FG4618 PCB Ver 0-00
Document Number:
Date: 26-Oct-2006
Sheet: 1/1
VER:
+
+
+
+
A1
C9
C10
C8
C13
C6
C2
1
2
H2
3
4
5
6
7
8
1
2
H3
3
4
5
6
7
8
1
2
H4
3
4
5
6
7
8
1
2
H7
3
4
5
6
7
8
1
2
H6
3
4
5
6
7
8
1
2
H8
3
4
5
6
7
8
C12
1
BATT
2
P1.0/TACLK/ACLK/A0+
2
P1.1/TA0/A0-/A4+
3
P1.2/TA1/A1+/A4-
4
P1.3/VREF/A1-
5
P1.4/SMCLK/A2+/TCK
6
P1.5/TA0/A2-/SCLK/TMS
7
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
8
P1.7/A3-/SDI/SDA/TDO/TDI
9
VCC
1
VSS
14
TEST/SBWTCK
11
XIN/P2.6/TA1
13
XOUT/P2.7
12
NMI/RST/SBWTDIO
10
U4
LED3
LE
D
4
1
JP3
2
1
JP
2
2
2
1
S
P
1
1 JP1
2
1
2
3
VCC_1
C
1
8
1
2
H5
3
4
C19
C
2
1
1
JP4
2
C1
1
2
H9
3
4
5
6
1
2
M
1
+
-
B
1
7F_7G_7E_DP7
P$1
7A_7B_7C_7D
P$2
6F_6G_6E_DP6
P$3
6A_6B_6C_6D
P$4
5F_5G_5E_COL5
P$5
5A_5B_5C_5D
P$6
4F_4G_4E_DP4
P$7
4A_4B_4C_4D
P$8
3F_3G_3E_COL3
P$9
3A_3B_3C_3D
P$10
2F_2G_2E_DP2
P$11
2A_2B_2C_2D
P$12
1F_1G_1E_DP1
P$13
1A_1B_1C_1D
P$14
COM3
P$15
COM2
P$16
COM1
P$17
COM0
P$18
F5_PR_P4_P3
P$19
F1_F2_F3_F4
P$20
PL_P0_P1_P2
P$21
AU_AR_AD_AL
P$22
BT_B1_B0_BB
P$23
ANT_A2_A1_A0
P$24
ENV_TX_RX_8BC
P$25
DOL_ERR_MINUS_MEM
P$26
1
3
5
7
9
JTAG2
11
13
2
4
6
12
14
8
10
1
3
5
7
9
JTAG1
11
13
2
4
6
12
14
8
10
1
6
2
7
3
8
4
9
5
RS232
G1
G2
C3
D2
D
1
2
3
7
8
5
6
U2
2
3
7
8
5
6
U1
Q1
1
2
S
1
1
2
S
2
R
3
3
R
3
1
R
2
6
R
2
7
R
3
4
R29
R32
R30
R
1
9
R
1
8
R20
R
1
3
R
1
4
R
1
5
R
1
6
R
2
3
R8
R
3
R10
R
1
R
2
R5
R9
R
4
R
1
1
R
1
2
R
1
7
1
PWR2
2
1
P
W
R
1
2
8
0
7
9
7
8
7
7
7
6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
LE
D
1
R
6
LE
D
2
R
7
R
2
8
C4
D
3
X
1
X2
C15
1
2
BB3
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
C5
C7
1
2
BB1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
BB2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
B
A
N
D
P
$
4
T
IP
P
$
1
R
IN
G
P
$
2
1
2
H1
3
4
5
6
7
8
11
11
12
12
13
13
14
14
1
1
2
2
15
15
16
16
4
4
5
5
6
6
7
7
8
8
9
9
10
10
3
3
INNER_GND
INNER_GND
C11
C16
C17
R24
R25
1
2
3
VCC_2
R21
R22
C
1
4
C
2
0
1
3
5
2
4
6
7
9
8
10
11
13
15
12
14
16
17
19
RF1
18
20
1
3
5
2
4
6
7
9
8
10
11
13
15
12
14
16
17
19
RF2
18
20
GND
S0
S0
S1
S1
S2
S2
S3
S3
S5
S5
S6
S6
S7
S7
S8
S8
S9
S9
S10
S
1
0
S11
S
1
1
S12
S
1
2
S13
S
1
3
S14
S
1
4
S4
S4
S15
S
1
5
S16
S
1
6
S17
S
1
7
S18
S
1
8
S19
S
1
9
S20
S
2
0
COM3
COM3
COM2
COM2
COM1
COM1
COM0
COM0
UCB0SDA
UCB0SDA
UCB0SDA
UCB0SCL
UCB0SCL
UCB0SCL
DVCC_4618
DVCC_4618
DVCC_4618
DVCC_4618
DVCC_4618
DVCC_4618
DVCC_4618
SIMO1
S
IM
O
1
SIMO1
SOMI1
SOMI1
S
O
M
I1
UCLK1
U
C
LK
1
UCLK1
S21
S
2
1
GDO2
GDO2
G
D
O
2
GDO0
GDO0
G
D
O
0
P3.0
P3.0
P3.0
UTXD1
UTXD1
URXD1
URXD1
P7.5
P
7
.5
2013_P1.2
2013_P1.3
2013_P1.4
2013_P1.5
SCL
SDA
2013_P2.7
2013_P2.6
SBWTCK
SBWTCK
SBWTDIO
SBWTDIO
P6.0
P6.0
P
6
.0
P6.1
P6.1
P
6
.1
P6.2
P6.2
P
6
.2
P6.5
P6.5
P6.5
LCDCAP
LCDCAP
P10.7
P10.7
P5.1
P5.1
VEREF+
VEREF+
RESETCC
RESETCC
R
ES
ET
C
C
VREG_EN
VREG_EN
V
R
EG
_E
N
FIFO
FIFO
FI
FO
FIFOP
FIFOP
FI
FO
P
PC_GND
2013_P1.1
2013_P1.0
P2.0
P
2
.0
P2.2
P
2
.2
P2.6
P2.6
UCB0CLK
UCB0CLK
UCB0CLK
P3.4
P3.4
P3.5
P3.5
P3.5
P3.7
P3.7
P5.6
P5.6
P7.4
P
7
.4
P7.6
P
7
.6
P7.7
P
7
.7
VREF
VREF
P5.0
P5.0
P10.6
P10.6
P6.4
P6.4
P6.4
P6.6
P6.6
P6.3
P6.3
P6.3
P6.7
P6.7
P6.7
VEREF-
VEREF-
SW1
S
W
1
SW1
SW2
S
W
2
SW2
P2.1
P
2
.1
P2.3
P
2
.3
P2.3
P2.7
P2.7
UCA0TXD
UCA0TXD
UCA0TXD
UCA0RXD
UCA0RXD
UCA0RXD
P3.6
P3.6
P5.7
P5.7
P5.5
P5.5
P4.2
P4.2
P4.2
P
7
.0
P7.0
U
C
A
0
S
IM
O
UCA0SIMO
U
C
A
0
S
O
M
I
UCA0SOMI
U
C
A
0
C
LK
UCA0CLK
P
4
.7
P4.7
P
4
.6
P4.6
LCL_PWR1
LCL_PWR1
FET_PWR1
FET_PWR1
FET_PWR2
FET_PWR2
LCL_PWR2
LCL_PWR2
AVCC_4618
AVCC_4618
0.1uF
10uF
0.1uF
0.1uF
0.1uF
GND
GND
VCC
0.1uF
GND
GND
0.1uF
GND
VCC
GND
MSP430F2013PW
G
N
D
GND
GND
A
L6
0
P
4
7
0n
GND
10uF
15
p
GND
VCC
0.1uF
GND
GND
10uF
1N4148
1
N
4
1
4
8
PS8802
PS8802
MMBT5088
GND
GND
VCC
GND
GND
1
0k
4
7
0k
47
0
1k
3
k3
1k
0
150k
1
0
4
7k
470
5
M
1
5
M
1
5
M
1
5
M
1
4
7
0
10
4
7
k
10
1
k
2
k2
100
2k2
2
k2
10
0
k
10
0
k
4
70
GND
V
C
C
_2
0
1
3
GND
4
7
0
GND
4
7
0
2
2k
10uF
1
N
4
1
4
8
10uF
10uF
10uF
VCC
VCC
1uF
22nF
3.3nF
1.4k
15.4k
0-DNP
0-DNP
D
N
P
47
0
n
G
N
D
GND
GND
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Schematic
11
SLAU213B – March 2007 – Revised August 2018
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Copyright © 2007–2018, Texas Instruments Incorporated
MSP430FG4618/F2013 Experimenter Board (MSP
‑
EXP430FG4618)
8
Schematic
Figure 7. MSP-EXP430FG4618 Schematic
