Description
If P1.1/P1.2 is pulled up externally to DVCC during power-up the logical HIGH value might
not be read correct by the device (ZERO is read instead of ONE).
Workaround
1) Switch the P1.1/P1.2 Port to logical ZERO after power cycle by:
a) Switch critical GPIO to output-low (with series resistance to limit current) or
b) Remove external pull up connection to pull GPIO via internal pull-down
OR
2) Use different GPIOs (not P1.1 & P1.2)
OR
3) Change the polarity of the logical check in SW (enable internal pull-up resistor for the
GPIO and pull the external pin to DVSS)
RTC8
RTC Module
Category
Functional
Function
RTC calendar tamper detection feature fails when DVCC and AUXVCC1 off.
Description
When DVCC and AUXVCC1 are off, the tamper detection function triggered by RTCCAP0
and RTCCAP1 pins cannot get a correct time stamp value.
Workaround
None
SD3
SD Module
Category
Functional
Function
Incorrect conversion result in twos complement mode when -VFS is applied
Description
When the SD converter is configured in twos complement mode with left or right
alignment and any OSR setting, applying the -VFS voltage at the input will result in an
erroneous output.
Workaround
None.
SYS16
SYS Module
Category
Functional
Function
Fast Vcc ramp after device power up may cause a reset
Description
At initial power-up, after Vcc crosses the brownout threshold and reaches a constant
level, an abrupt ramp of Vcc at a rate dV/dT > 1V/100us can cause a brownout condition
to be incorrectly detected even though Vcc does not fall below the brownout threshold.
This causes the device to undergo a reset.
Workaround
Use a controlled Vcc ramp to power up the device.
UCS11
UCS Module
Category
Functional
Function
Modifying UCSCTL4 clock control register triggers an additional erroneous clock request
Advisory Descriptions
22
MSP430F67691 Microcontroller
SLAZ509AC – JANUARY 2013 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
