OR
The SPI master must set the clock pin at the appropriate idle level (low for UCCKPL = 0,
high for UCCKPL = 1) before SPI slave is reset (UCSWRST bit is cleared).
OR
For eUSCI_A: to detect communication failure condition where UCRXIFG is not set, check
both UCRXIFG and UCTXIFG. If UCTXIFG is set twice but UCRXIFG is not set, reset the
MSP SPI slave by setting and then clearing the UCSWRST bit, and inform the SPI master
to resend the data.
USCI50
USCI Module
Category
Functional
Function
Data may not be transmitted correctly from the eUSCI when operating in SPI 4-pin master
mode with UCSTEM = 0
Description
When the eUSCI is used in SPI 4-pin master mode with UCSTEM = 0 (STE pin used as
an input to prevent conflicts with other SPI masters), data that is moved into UCxTXBUF
while the UCxSTE input is in the inactive state may not be transmitted correctly. If the
eUSCI is used with UCSTEM = 1 (STE pin used to output an enable signal), data is
transmitted correctly.
Workaround
When using the STE pin in conflict prevention mode (UCSTEM = 0), only move data
into UCxTXBUF when UCxSTE is in the active state. If an active transfer is aborted
by UCxSTE transitioning to the master-inactive state, the data must be rewritten into
UCxTXBUF to be transferred when UCxSTE transitions back to the master-active state.
Advisory Descriptions
SLAZ481AD – DECEMBER 2012 – REVISED MAY 2021
MSP430F6767 Microcontroller
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