Description
Device may not wake up from LPM2, LPM3 or LMP4 if an interrupt occurs within 1
us after the entry to the specified LPMx; entry can be caused either by user code or
automatically (for example, after a previous ISR is completed). Device can be recovered
with an external reset or a power cycle. Additionally, a PUC can also be used to reset
the failing condition and bring the device back to normal operation (for example, a PUC
caused by the WDT).
This effect is seen when:
- A write to the SVSMHCTL and SVSMLCTL registers is immediately followed
by an LPM2, LPM3, LPM4 entry without waiting the requisite settling time
((PMMIFG.SVSMLDLYIFG = 0 and PMMIFG.SVSMHDLYIFG = 0)).
or
The following two conditions are met:
- The SVSL module is configured for a fast wake-up or when the SVSL/SVML module is
turned off. The affected SVSMLCTL register settings are shaded in the following table.
and
-The SVSH/SVMH module is configured to transition from Normal mode to an OFF
state when moving from Active/LPM0/LPM1 into LPM2/LPM3/LPM4 modes. The affected
SVSMHCTL register settings are shaded in the following table.
Workaround
Any write to the SVSMxCTL register must be followed by a settling delay
(PMMIFG.SVSMLDLYIFG = 0 and PMMIFG.SVSMHDLYIFG = 0) before entering LPM2,
LPM3, LPM4.
Advisory Descriptions
18
MSP430F67621 Microcontroller
SLAZ607V – AUGUST 2014 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
