Function
MCLK comes up fast on exit from LPM3 and LPM4
Description
The DCO exceeds the programmed frequency of operation on exit from LPM3 and
LPM4 for up to 6 us. This behavior is masked from affecting code execution by default:
SVSL and SVML run in normal-performance mode and mask CPU execution for 150
us on wakeup from LPM3 and LPM4. However ,when the low-side SVS and the SVM
are disabled or are operating in full-performance mode (SVMLE= 0 and SVSLE= 0, or
SVMLFP= 1 and SVSLFP= 1) AND MCLK is sourced from the internal DCO running over
4 MHz, 7 MHz,11 MHz,or 14 MHz at core voltage levels 0, 1, 2, and 3, respectively, the
mask lasts only 2 us. MCLK is, therefore, susceptible to run out of spec for 4 us.
Workaround
Set the MCLK divide bits in the Unified Clock System Control 5 Register (UCSCTL5) to
divide MCLK by two prior to entering LPM3 or LPM4 (set DIVMx= 001). This prevents
MCLK from running out of spec when the CPU wakes from the low-power mode.
Following the wakeup fromthe low-power mode, wait 32, 48, 80, or 100 cycles for core
voltage levels 0, 1, 2, and 3, respectively, before resetting DIVM xto zero and running
MCLK at full speed [for example, __delay_cycles(100)]
PMM12
PMM Module
Category
Functional
Function
SMCLK comesup fast on exit from LPM3 and LPM4
Description
The DCO exceeds the programmed frequency of operationon exit from LPM3 and LPM4
for up to 6 us. When SMCLK is sourced by the DCO, it is not masked on exit from LPM3
or LPM4. Therefore, SMCLK exceeds the programmed frequency of operation on exit
from LPM3 and LPM4 for up to 6 us. The increased frequency has the potential to change
the expected timing behavior of peripherals that select SMCLK as the clock source.
Workaround
- Use XT2 as the SMCLK oscillator source instead of the DCO
or
- Do not disable the clock request bit for SMCLKREQEN in the Unified Clock System
Control 8 Register (UCSCTL8). This means that all modules that depend on SMCLK to
operate successfully should be halted or disabled before entering LPM3 or LPM4. If the
increased frequency prevents the proper function of an affected module, wait 32, 48, 80
or 100 cycles for core voltage levels 0, 1, 2, or 3, respectively, before re-enabling the
module. (for example, __delay_cycles(100)
PMM14
PMM Module
Category
Functional
Function
Increasing the core level when SVS/SVM low side is configured in full-performance mode
causes device reset
Description
When the SVS/SVM low side is configured in full performance mode
(SVSMLCTL.SVSLFP = 1), the setting time delay for the SVS comparators is ~2us. When
increasing the core level in full-performance mode; the core voltage does not settle to the
new level before the settling time delay of the SVS/SVM comparator expires. This results
in a device reset.
Workaround
When increasing the core level; enable the SVS/SVM low side in normal mode
(SVSMLCTL.SVSLFP=0). This provides a settling time delay of approximately 150us
allowing the core sufficient time to increase to the expected voltage before the delay
expires.
Advisory Descriptions
SLAZ501AC – JANUARY 2013 – REVISED MAY 2021
MSP430F67461 Microcontroller
17
Copyright © 2021 Texas Instruments Incorporated
