Note
As soon the SVSL or the SVML is enabled in Normal performance mode the
device is in slow wakeup mode and this erratum does not apply. In addition, this
erratum has sporadic characteristic due to an internal asynchronous circuit. The
drop of Vcore does not have an impact on specified device performance.
Workaround
If SVSL or SVML is required for application (to observe external disruptive events at
Vcore pin) the slow wakeup mode has to be used to avoid unexpected SVSL/SVML
events. This is achieved if the SVSL or the SVML is configured in "Normal" performance
mode (not disabled and not in "Full" Performance Mode).
PMM26
PMM Module
Category
Functional
Function
Device lock-up if RST pin pulled low during write to SVSMHCTL or SVSMLCTL
Description
Device results in lock-up condition under one of the two scenarios below:
1) If RST pin is pulled low during write access to SVSMHCTL, with the RST/NMI pin
is configured to reset function and is pulled low (reset event) the device will stop code
execution and is continuously held in reset state. RST pin is no longer functional. The only
way to come out of the lock-up situation is a power cycle.
OR
2) If RST pin is pulled low during write access to SVSMLCTL and only if the code that
checks for SVSMLDLYIFG==1 is implemented without a timeout. The device will be stuck
in the polling loop polling since SVSMLDLYIFG will never be cleared.
Workaround
Follow the sequence below to prevent the lock-up for both use cases:
1) Disable RST pin reset function and switch to NMI before access SVSMHCTL or
SVSMLCTL.
then
2) Activate NMI interrupt and handle reset events in this time by SW (optional if reset
functionality required during access SVSMHCTL or SVSMLCTL)
then
3) Enable RST pin reset function after access to SVSMHCTL or SVSMLCTL
To prevent lock-up caused by use case #2 a timeout for the SVSMLDLYIFG flag check
should be implemented to 300us.
PORT15
PORT Module
Category
Functional
Function
In-system debugging causes the PMALOCKED bit to be always set
Description
The port mapping controller registers cannot be modified when single-stepping or halting
at break points between a valid password write to the PMAPWD register and the expected
lock of the port mapping (PMAP) registers. This causes the PMAPLOCKED bit to remain
set and not clear as expected.
Note: This erratum only applies to in-system debugging and is not applicable when
operating in free-running mode.
Advisory Descriptions
20
MSP430F6735A Microcontroller
SLAZ647S – FEBRUARY 2015 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
