Texas Instruments MSP430F6730, Manual

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Workaround For correct functional implementation check on transmit or receive interrupt flag
UCTXIFG/UCRXIFG instead of UCBUSY to know if the UCAxTXBUF buffer is empty or
ready for the next complete character.
To reduce the additional current it is recommended to either reset the SPI module
(UCAxCTLW0.UCSWRST) in the UCBxCTLW0 or send a dummy byte 0x00 after the
intended SPI transmission is completed.
USCI42
USCI Module
Category
Functional
Function UART asserts UCTXCPTIFG after each byte in multi-byte transmission
Description UCTXCPTIFG flag is triggered at the last stop bit of every UART byte transmission,
independently of an empty buffer, when transmitting multiple byte sequences via UART.
The erroneous UART behavior occurs with and without DMA transfer.
Workaround None.
USCI47
USCI Module
Category
Functional
Function eUSCI SPI slave with clock phase UCCKPH = 1
Description The eUSCI SPI operates incorrectly under the following conditions:
1. The eUSCI_A or eUSCI_B module is configured as a SPI slave with clock phase mode
UCCKPH = 1
AND
2. The SPI clock pin is not at the appropriate idle level (low for UCCKPL = 0, high for
UCCKPL = 1) when the UCSWRST bit in the UCxxCTLW0 register is cleared.
If both of the above conditions are satisfied, then the following will occur:
eUSCI_A: the SPI will not be able to receive a byte (UCAxRXBUF will not be filled and
UCRXIFG will not be set) and SPI slave output data will be wrong (first bit will be missed
and data will be shifted).
eUSCI_B: the SPI receives data correctly but the SPI slave output data will be wrong (first
byte will be duplicated or replaced by second byte).
Workaround Use clock phase mode UCCKPH = 0 for MSP SPI slave if allowed by the application.
OR
The SPI master must set the clock pin at the appropriate idle level (low for UCCKPL = 0,
high for UCCKPL = 1) before SPI slave is reset (UCSWRST bit is cleared).
OR
For eUSCI_A: to detect communication failure condition where UCRXIFG is not set, check
both UCRXIFG and UCTXIFG. If UCTXIFG is set twice but UCRXIFG is not set, reset the
MSP SPI slave by setting and then clearing the UCSWRST bit, and inform the SPI master
to resend the data.
www.ti.com Advisory Descriptions
SLAZ344AF – OCTOBER 2012 – REVISED MAY 2021
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