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PN80

LQFP (PN), 80 Pin

5.3 Memory-Mapped Hardware Revision (TLV Structure)

Die Revision

TLV Hardware Revision

Rev A

10h

Further guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User's
Guide.

Nomenclature, Package Symbolization, and Revision Identification

SLAZ341AF – OCTOBER 2012 – REVISED MAY 2021

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MSP430F6724 Microcontroller

5

Copyright © 2021 Texas Instruments Incorporated

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Summary of Contents for MSP430F6724

Page 1: ...dvisories 3 4 Fixed by Compiler Advisories 3 5 Nomenclature Package Symbolization and Revision Identification 4 5 1 Device Nomenclature 4 5 2 Package Markings 4 5 3 Memory Mapped Hardware Revision TLV Structure 5 6 Advisory Descriptions 6 7 Revision History 25 www ti com Table of Contents SLAZ341AF OCTOBER 2012 REVISED MAY 2021 Submit Document Feedback MSP430F6724 Microcontroller 1 Copyright 2021 ...

Page 2: ...M7 PMM11 PMM12 PMM14 PMM15 PMM18 PMM20 PMM26 PORT15 PORT19 SD3 UCS11 USCI36 USCI37 USCI41 USCI42 USCI47 USCI50 2 Preprogrammed Software Advisories Advisories that affect factory programmed software The check mark indicates that the issue is present in the specified revision Errata Number Rev A BSL7 BSL14 Functional Advisories www ti com 2 MSP430F6724 Microcontroller SLAZ341AF OCTOBER 2012 REVISED ...

Page 3: ... Number Rev A CPU21 CPU22 CPU40 Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds TI MSP430 Compiler Tools Code Composer Studio IDE MSP430 Optimizing C C Compiler Check the silicon_errata option MSP430 Assembly Language Tools MSP430 GNU Compiler MSP430 GCC MSP430 GCC Options Check msilicon errata and msilicon errata warn options MSP430 GCC User s ...

Page 4: ...esting null Fully qualified development support product XMS devices and X development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes MSP devices have been characterized fully and the quality and reliability of the device have been demonstrated fully TI s standard warranty applies Predictions show that prototype devices ...

Page 5: ...r guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User s Guide www ti com Nomenclature Package Symbolization and Revision Identification SLAZ341AF OCTOBER 2012 REVISED MAY 2021 Submit Document Feedback MSP430F6724 Microcontroller 5 Copyright 2021 Texas Instruments Incorporated ...

Page 6: ...el repeat sequence of channels ADC12CTL1 ADC12CONSEQx In addition the timer overflow flag cannot be used to detect an overflow ADC12IFGR2 ADC12TOVIFG Workaround 1 For manual trigger mode ADC12CTL0 ADC12SC ensure each ADC conversion is completed by first checking ADC12CTL1 ADC12BUSY bit before starting a new conversion 2 For timer trigger mode ADC12CTL1 ADC12SHP ensure the timer period is greater t...

Page 7: ...pply could be switched back to DVCC again When the system is running with the AUXVCC2 supply use SVMH to monitor AUXVCC2 voltage When AUXVCC2 is lower than the SVMH setting the program drives the chip into LPMx 5 After DVCC ramps up back again trigger one of the wake up pins The power supply could be switched back to DVCC again AUXPMM2 AUXPMM Module Category Functional Function Latch up in AUXPMM ...

Page 8: ...rio 2 Limit the supply voltage ramp up time through a series resistor e g 10 Ohm in the critical supply path Side effects such as voltage dips due to high current consumption of the device need to be considered BSL7 BSL Module Category Software in ROM Function BSL does not start after waking up from LPMx 5 Description When waking up from LPMx 5 mode the BSL does not start as it does not clear the ...

Page 9: ...xpected results Description When using the indirect addressing mode in an instruction with the Program Counter PC as the source operand the instruction that follows immediately does not get executed For example in the code below the ADD instruction does not get executed mov PC R7 add 1h R4 Workaround Refer to the table below for compiler specific fix implementation information IDE Compiler Version...

Page 10: ...ode with instruction that contains PC as destination register or the data section Refer to the table below for compiler specific fix implementation information IDE Compiler Version Number Notes IAR Embedded Workbench IAR EW430 v5 51 or later For the command line version add the following information Compiler hw_workaround CPU40 Assembler v1 TI MSP430 Compiler Tools Code Composer Studio v4 0 x or l...

Page 11: ... assembler is required to implement the above workaround manually TI MSP430 Compiler Tools Code Composer Studio Not affected C code is not impacted by this bug User using POPM instruction in assembler is required to implement the above workaround manually MSP430 GNU Compiler MSP430 GCC Not affected C code is not impacted by this bug User using POPM instruction in assembler is required to implement...

Page 12: ...alues lower 64K of Flash DMA7 DMA Module Category Functional Function DMA request may cause the loss of interrupts Description If a DMA request starts executing during the time when a module register containing an interrupt flags is accessed with a read modify write instruction a newly arriving interrupt from the same module can get lost An interrupt flag set prior to DMA execution would not be af...

Page 13: ...he DMA Description In repeated transfer mode the DMA automatically reloads the size counter DMAxSZ once a transfer is complete and immediately continues to execute the next transfer unless the DMA Enable bit DMAEN has been previously cleared In burst block transfer mode DMA block transfers are interleaved with CPU activity 80 20 of ten CPU cycles eight are allocated to a block transfer and two are...

Page 14: ...a breakpoint is hit or when the debug session is halted Workaround This erratum has been addressed in MSPDebugStack version 3 5 0 1 It is also available in released IDE EW430 IAR version 6 30 3 and CCS version 6 1 1 or newer If using an earlier version of either IDE or MSPDebugStack do not halt or use breakpoints during a DMA transfer Note This erratum applies to debug mode only EEM23 EEM Module C...

Page 15: ... as MSP430 DLL v3 4 3 4 OR b Roll back the debug stack by either performing a clean re installation of a previous version of the IDE or by manually replacing the debug stack with a prior version such as MSP430 DLL v3 4 3 4 that can be obtained from http www ti com tool MSPDS 2 In case JTAG connectivity fails during the LPMx 5 debug mode the device supply voltage level needs to be raised or lowered...

Page 16: ... 1 PMM7 PMM Module Category Functional Function PMMRIE default conditions different than user guide Description The user guide specifies that after a BOR reset condition the SVS will not be configured to trigger a POR signal in the condition that the monitored voltages fall below the SVS level s This is not true for this device The SVS Low and SVS High Side POR Enable bits SVSLPE SVSHPE in the Pow...

Page 17: ...for SMCLKREQEN in the Unified Clock System Control 8 Register UCSCTL8 This means that all modules that depend on SMCLK to operate successfully should be halted or disabled before entering LPM3 or LPM4 If the increased frequency prevents the proper function of an affected module wait 32 48 80 or 100 cycles for core voltage levels 0 1 2 or 3 respectively before re enabling the module for example __d...

Page 18: ...time PMMIFG SVSMLDLYIFG 0 and PMMIFG SVSMHDLYIFG 0 or The following two conditions are met The SVSL module is configured for a fast wake up or when the SVSL SVML module is turned off The affected SVSMLCTL register settings are shaded in the following table and The SVSH SVMH module is configured to transition from Normal mode to an OFF state when moving from Active LPM0 LPM1 into LPM2 LPM3 LPM4 mod...

Page 19: ...TL SVMLE SVSMLCTL SVMLE SVSMLCTL SVMLFP Next Check SVSH SVMH settings to see if settings are affected by PMM15 if SVSMHCTL SVSHE SVSMHCTL SVSHFP if SVSMHCTL SVSHMD SVSMHCTL SVSHMD SVSMHCTL SVSMHACE return 1 SVSH affected configurations if SVSMHCTL SVMHE SVSMHCTL SVMHFP SVSMHCTL SVSMHACE return 1 SVMH affected configurations return 0 SVS M settings not affected by PMM15 2 If fast servicing of inter...

Page 20: ...achieved if the SVSL or the SVML is configured in Normal performance mode not disabled and not in Full Performance Mode PMM26 PMM Module Category Functional Function Device lock up if RST pin pulled low during write to SVSMHCTL or SVSMLCTL Description Device results in lock up condition under one of the two scenarios below 1 If RST pin is pulled low during write access to SVSMHCTL with the RST NMI...

Page 21: ... 5 it is possible that the interrupt is lost Hence this interrupt will not trigger a wakeup from LPMx 5 Workaround None SD3 SD Module Category Functional Function Incorrect conversion result in twos complement mode when VFS is applied Description When the SD converter is configured in twos complement mode with left or right alignment and any OSR setting applying the VFS voltage at the input will r...

Page 22: ...a potential RXBUF overflow If this flag is cleared with a read access from the RXBUF register during a falling edge of SCL the clear condition might be missed This could result in an I2C bus stall at the next received byte Workaround 1 Execute two consecutive reads of RXBUF if tSCL 4 x tMCLK or 2 Provoke an I2C bus stall before reading RXBUF A bus stall can be verified by checking if the clock lin...

Page 23: ...I clock pin is not at the appropriate idle level low for UCCKPL 0 high for UCCKPL 1 when the UCSWRST bit in the UCxxCTLW0 register is cleared If both of the above conditions are satisfied then the following will occur eUSCI_A the SPI will not be able to receive a byte UCAxRXBUF will not be filled and UCRXIFG will not be set and SPI slave output data will be wrong first bit will be missed and data ...

Page 24: ...f the eUSCI is used with UCSTEM 1 STE pin used to output an enable signal data is transmitted correctly Workaround When using the STE pin in conflict prevention mode UCSTEM 0 only move data into UCxTXBUF when UCxSTE is in the active state If an active transfer is aborted by UCxSTE transitioning to the master inactive state the data must be rewritten into UCxTXBUF to be transferred when UCxSTE tran...

Page 25: ...4 2019 to May 19 2021 Page Changed the document format and structure updated the numbering format for tables figures and cross references throughout the document 6 www ti com Revision History SLAZ341AF OCTOBER 2012 REVISED MAY 2021 Submit Document Feedback MSP430F6724 Microcontroller 25 Copyright 2021 Texas Instruments Incorporated ...

Page 26: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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