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Texas Instruments MSP430F2232IDA, User Manual

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Texas Instruments MSP430F2232IDA User Manual Download Page 67

LFXT1 off

P2SEL.7

Bus

Keeper

EN

Direction
0: Input
1: Output

P2SEL.6

1

0

P2DIR.6

P2IN.6

P2IRQ.6

D

EN

Module X IN

1

0

Module X OUT

P2OUT.6

Interrupt

Edge

Select

Q

EN

Set

P2SEL.6

P2IES.6

P2IFG.6

P2IE.6

P2.6/XIN

1

0

DVSS

DVCC

P2REN.6

Pad Logic

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

P2.7/XOUT

0

1

1

LFXT1CLK

MSP430F22x2
MSP430F22x4

www.ti.com

SLAS504G – JULY 2006 – REVISED AUGUST 2012

Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input

Table 29. Port P2 (P2.6) Pin Functions

CONTROL BITS/SIGNALS

(1)

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

P2SEL.x

P2.6 (I/O)

I: 0; O: 1

0

P2.6/XIN

6

XIN

(2)

X

1

(1)

X = Don't care

(2)

Default after reset (PUC/POR)

Copyright © 2006–2012, Texas Instruments Incorporated

67

Summary of Contents for MSP430F2232IDA

Page 1: ...KB 256B Flash Memory Registers 512B RAM 16 Bit Timer_B With Three Capture Compare MSP430F2254 Registers 16KB 256B Flash Memory Universal Serial Communication Interface 512B RAM Enhanced UART Supportin...

Page 2: ...2x4 devices and 32 I O pins Typical applications include sensor systems that capture analog signals convert them to digital values and then process the data for display or for transmission to a host s...

Page 3: ...A15 OA1I3 DVSS P4 5 TB2 A14 OA0I3 1 TEST SBWTCK 2 DVCC 3 P2 5 ROSC 4 XOUT P2 7 5 XIN P2 6 6 RST NMI SBWTDIO 7 P2 0 ACLK A0 8 P2 1 TAINCLK SMCLK A1 9 P2 2 TA0 A2 10 P3 0 UCB0STE UCA0CLK A5 11 P3 1 UCB0...

Page 4: ...0 P2 1 TAINCLK SMCLK A1 P2 2 TA0 A2 P3 0 UCB0STE UCA0CLK A5 P3 1 UCB0SIMO UCB0SDA DVCC P1 7 TA2 TDO TDI P2 3 TA1 A3 VREF VeREF P3 7 A7 P3 6 A6 P3 5 UCA0RXD UCA0SOMI P3 4 UCA0TXD UCA0SIMO AVCC AVSS P3...

Page 5: ...1 OA0O P2 2 TA0 A2 OA0I1 P3 0 UCB0STE UCA0CLK A5 P3 1 UCB0SIMO UCB0SDA DVCC P1 7 TA2 TDO TDI P2 3 TA1 A3 VREF VeREF OA1I1 OA1O P3 7 A7 OA1I2 P3 6 A6 OA0I2 P3 5 UCA0RXD UCA0SOMI P3 4 UCA0TXD UCA0SIMO A...

Page 6: ...006 REVISED AUGUST 2012 www ti com MSP430F22x4 MSP430F22x2 Device Pinout YFF Package Package Dimensions The package dimensions for this YFF package are shown in Table 2 See the package drawing at the...

Page 7: ...P4 x 2x8 Basic Clock System RAM 1kB 512B 512B Brownout Protection RST NMI VCC VSS MCLK SMCLK Watchdog WDT 15 16 Bit Timer_A3 3 CC Registers 16MHz CPU incl 16 Registers Emulation 2BP XOUT JTAG Interfac...

Page 8: ...lock Input for programming and test General purpose digital I O pin P1 7 TA2 TDO TDI 1 D2 38 36 I O Timer_A compare OUT2 output Test Data Output or Test Data Input for programming and test General pur...

Page 9: ...a input UCA0SOMI USCI_A0 SPI mode slave out master in General purpose digital I O pin P3 6 A6 F4 27 25 I O ADC10 analog input A6 General purpose digital I O pin P3 7 A7 G4 28 26 I O ADC10 analog input...

Page 10: ...e test data input output during programming and test Selects test mode for JTAG pins on Port 1 The device protection fuse is connected to TEST TEST SBWTCK D1 1 37 I Spy Bi Wire test clock input during...

Page 11: ...General purpose digital I O pin P1 6 TA1 TDI TCLK E3 37 35 I O Timer_A compare OUT1 output Test Data Input or Test Clock Input for programming and test General purpose digital I O pin P1 7 TA2 TDO TD...

Page 12: ...SCI_B0 SPI mode slave out master in USCI_B0 I2C mode SCL I2C clock General purpose digital I O pin P3 3 UCB0CLK UCA0STE B6 14 12 I O USCI_B0 clock input output USCI_A0 slave transmit enable General pu...

Page 13: ...O pin Timer_B switch all TB0 to TB3 outputs to high impedance P4 6 TBOUTH A15 OA1I3 G7 23 21 I O ADC10 analog input A15 OA1 analog input I3 General purpose digital I O pin P4 7 TBCLK F5 24 22 I O Tim...

Page 14: ...as program counter stack pointer status register and constant generator respectively The remaining registers are general purpose registers Peripherals are connected to the CPU using data address and...

Page 15: ...active Low power mode 0 LPM0 CPU is disabled ACLK and SMCLK remain active MCLK is disabled Low power mode 1 LPM1 CPU is disabled ACLK and SMCLK remain active MCLK is disabled DCO dc generator is disa...

Page 16: ...IFG maskable 0FFF0h 24 TAIFG 2 4 USCI_A0 USCI_B0 Receive UCA0RXIFG UCB0RXIFG 2 maskable 0FFEEh 23 USCI_A0 USCI_B0 Transmit UCA0TXIFG UCB0TXIFG 2 maskable 0FFECh 22 ADC10 ADC10IFG 4 maskable 0FFEAh 21...

Page 17: ...upt Enable 2 Address 7 6 5 4 3 2 1 0 01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw 0 rw 0 rw 0 rw 0 UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transmit interrupt enable UCB0RXIE USCI_B0 r...

Page 18: ...es of the BSL and its implementation see the MSP430 Programming Via the Bootstrap Loader User s Guide SLAU319 Table 13 BSL Function Pins BSL FUNCTION DA PACKAGE PINS RHA PACKAGE PINS YFF PACKAGE PINS...

Page 19: ...ENCY CALIBRATION REGISTER SIZE ADDRESS CALBC1_1MHZ byte 010FFh 1 MHz CALDCO_1MHZ byte 010FEh CALBC1_8MHZ byte 010FDh 8 MHz CALDCO_8MHZ byte 010FCh CALBC1_12MHZ byte 010FBh 12 MHz CALDCO_12MHZ byte 010...

Page 20: ...NPUT INPUT OUTPUT BLOCK DA RHA YFF DA RHA YFF SIGNAL NAME SIGNAL 31 P1 0 29 P1 0 F2 P1 0 TACLK TACLK Timer NA ACLK ACLK SMCLK SMCLK 9 P2 1 7 P2 1 B4 P2 1 TAINCLK INCLK 32 P1 1 30 P1 1 G2 P1 1 TA0 CCI0...

Page 21: ...TB1 CCI1A CCR1 TB1 18 P4 1 16 P4 1 D7 P4 1 21 P4 4 19 P4 4 F7 P4 4 TB1 CCI1B 21 P4 4 19 P4 4 F7 P4 4 VSS GND VCC VCC 19 P4 2 17 P4 2 E6 P4 2 TB2 CCI2A CCR2 TB2 19 P4 2 17 P4 2 E6 P4 2 ACLK CCI2B 22 P...

Page 22: ...ior to analog to digital conversion Table 17 OA0 Signal Connections ANALOG INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME DA RHA YFF 8 A0 6 A0 B4 A0 OA0I0 OAxI0 10 A2 8 A2 B5 A2 OA0I1 OA0I1 10...

Page 23: ...1 0194h Capture compare register TBCCR0 0192h Timer_B register TBR 0190h Capture compare control TBCCTL2 0186h Capture compare control TBCCTL1 0184h Capture compare control TBCCTL0 0182h Timer_B contr...

Page 24: ...UCA0MCTL 064h USCI_A0 baud rate control 1 UCA0BR1 063h USCI_A0 baud rate control 0 UCA0BR0 062h USCI_A0 control 1 UCA0CTL1 061h USCI_A0 control 0 UCA0CTL0 060h USCI_A0 IrDA receive control UCA0IRRCTL...

Page 25: ...ort P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1...

Page 26: ...he voltage is applied to the TEST pin when blowing the JTAG fuse 3 Higher temperature may be applied during board soldering process according to the current JEDEC J STD 020 specification with peak ref...

Page 27: ...CTL CALDCO_1MHZ CPUOFF 0 SCG0 0 SCG1 0 OSCOFF 0 fMCLK fSMCLK fACLK 32768 Hz 8 40 C to 5 9 4096 Hz 85 C 2 2 V fDCO 0 Hz 105 C 18 Active mode AM Program executes in flash IAM 4kHz A 40 C to current 4 kH...

Page 28: ...0 fDCO DCO Frequency MHz Active Mode Current mA TA 25 C TA 85 C VCC 2 2 V VCC 3 V TA 25 C TA 85 C MSP430F22x2 MSP430F22x4 SLAS504G JULY 2006 REVISED AUGUST 2012 www ti com Typical Characteristics Act...

Page 29: ...4 2 2 V 85 C 2 4 3 3 fDCO fMCLK fSMCLK 0 MHz 105 C 5 10 Low power mode 3 fACLK 32768 Hz ILPM3 LFXT1 A LPM3 current 4 CPUOFF 1 SCG0 1 40 C 0 9 1 5 SCG1 1 OSCOFF 0 25 C 0 9 1 5 3 V 85 C 2 6 3 8 105 C 6...

Page 30: ...air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Port P1 P2 P1 x to P2 x External trigger t int External interrupt timing 2 2 V 3 V 20 ns pulse width to set inter...

Page 31: ...mA to hold the maximum voltage drop specified 2 The maximum total current IOH max and IOL max for all outputs combined should not exceed 48 mA to hold the maximum voltage drop specified Output Frequen...

Page 32: ...vel Output Current mA VOL Low Level Output V oltage V 0 0 10 0 20 0 30 0 40 0 50 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 VCC 3 V P4 5 TA 25 C TA 85 C OL I Typical Low Level Output Current mA MSP430F22x2 MSP...

Page 33: ...t 3 V s 70 130 210 mV td BOR See Figure 8 2000 s Pulse length needed at RST NMI pin t reset 3 V 2 s to accepted reset internally 1 The current consumption of the brownout module is already included in...

Page 34: ...1 ns tpw Pulse Width s V CC drop V tpw Pulse Width s VCC 3 V MSP430F22x2 MSP430F22x4 SLAS504G JULY 2006 REVISED AUGUST 2012 www ti com Typical Characteristics POR Brownout Reset BOR Figure 9 VCC drop...

Page 35: ...3 DCOx 3 MODx 0 2 2 V 3 V 0 20 0 40 MHz fDCO 4 3 DCO frequency 4 3 RSELx 4 DCOx 3 MODx 0 2 2 V 3 V 0 28 0 54 MHz fDCO 5 3 DCO frequency 5 3 RSELx 5 DCOx 3 MODx 0 2 2 V 3 V 0 39 0 77 MHz fDCO 6 3 DCO...

Page 36: ...over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1 MHz tolerance over 0 C to 85 C 3 V 2 5 0 5 2 5 t...

Page 37: ...Hz Gating time 2 ms Calibrated DCO Frequencies Overall Tolerance over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS TA VCC MI...

Page 38: ...00 1 01 1 02 1 03 1 5 2 0 2 5 3 0 3 5 4 0 Frequency MHz TA 40 C TA 25 C TA 85 C TA 105 C MSP430F22x2 MSP430F22x4 SLAS504G JULY 2006 REVISED AUGUST 2012 www ti com Typical Characteristics Calibrated 1...

Page 39: ...CALDCO_8MHZ DCO clock wake up time tDCO LPM3 4 s from LPM3 4 1 BCSCTL1 CALBC1_12MHZ 1 DCOCTL CALDCO_12MHZ BCSCTL1 CALBC1_16MHZ 3 V 1 DCOCTL CALDCO_16MHZ CPU wake up time from 1 fMCLK tCPU LPM3 4 LPM3...

Page 40: ...ternal Resistor ROSC 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DCOR 1 2 2 V 1 8 fDCO ROSC DCO...

Page 41: ...N and XOUT pins f If conformal coating is used ensure that it does not induce capacitive or resistive leakage between the oscillator pins g Do not route the XOUT line to the JTAG header to support the...

Page 42: ...be observed a Keep the trace between the device and the crystal as short as possible b Design a good ground plane around the oscillator pins c Prevent crosstalk from other clock or data lines into os...

Page 43: ...A 25 C CL eff 15 pF TA 25 C Figure 18 Figure 19 Timer_A over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UN...

Page 44: ...put data hold time ns 3 V 0 2 2 V 30 UCLK edge to SIMO valid tVALID MO SIMO output data valid time ns CL 20 pF 3 V 20 1 fUCxCLK 1 2tLO HI with tLO HI max tVALID MO USCI tSU SI Slave tSU MI USCI tVALID...

Page 45: ...MO UCLK CKPL 0 CKPL 1 SIMO 1 fUCxCLK tLO HI tLO HI SOMI tSU MI tHD MI tVALID MO MSP430F22x2 MSP430F22x4 www ti com SLAS504G JULY 2006 REVISED AUGUST 2012 Figure 20 SPI Master Mode CKPH 0 Figure 21 SPI...

Page 46: ...CLK STE UCLK CKPL 0 CKPL 1 SOMI tSTE ACC tSTE DIS 1 fUCxCLK tLO HI tLO HI SIMO tSU SI tHD SI tVALID SO tSTE LEAD tSTE LAG MSP430F22x2 MSP430F22x4 SLAS504G JULY 2006 REVISED AUGUST 2012 www ti com Figu...

Page 47: ...lock frequency External UCLK fSYSTEM MHz Duty cycle 50 10 fSCL SCL clock frequency 2 2 V 3 V 0 400 kHz fSCL 100 kHz 4 tHD STA Hold time repeated START 2 2 V 3 V s fSCL 100 kHz 0 6 fSCL 100 kHz 4 7 tSU...

Page 48: ...rence buffer supply ADC10ON 0 REFON 1 IREFB 0 current with mA REF2_5V 0 REFOUT 1 105 C 2 2 V 3 V 1 8 ADC10SR 0 4 ADC10SR 0 fADC10CLK 5 MHz 40 C to 85 C 2 2 V 3 V 0 5 0 7 Reference buffer supply ADC10O...

Page 49: ...ror of conversion result ADC10SR 1 2000 time 1 LSB Maximum IVREF 1 mA CVREF capacitance at pin 2 2 V 3 V 100 pF REFON 1 REFOUT 1 VREF 1 Temperature IVREF constant with TCREF 2 2 V 3 V 100 ppm C coeffi...

Page 50: ...cy requirements 3 Under this condition the external reference is internally buffered The reference buffer is active and requires the reference buffer supply current IREFB The current consumption can b...

Page 51: ...44 3 55 3 66 mV C VOffset Sensor Sensor offset voltage ADC10ON 1 INCHx 0Ah 2 100 100 mV Temperature sensor voltage at 1265 1365 1465 TA 105 C T version only Temperature sensor voltage at TA 85 C 1195...

Page 52: ...to 105 C 50 50 Fast Mode 50 Medium Mode fV I P 1 kHz 80 Slow Mode 140 Voltage noise Vn nV Hz density I P Fast Mode 30 Medium Mode fV I P 10 kHz 50 Slow Mode 65 VIO Offset voltage I P 2 2 V 3 V 10 mV O...

Page 53: ...s of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Fast Mode 1 2 SR Slew rate Medium Mode 0 8 V s Slow Mode 0 3 Open loop volt...

Page 54: ...ature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT OAFBRx 1 OARRIP 0 0 245 0 25 0 255 OAFBRx 2 OARRIP 0 0 495 0 5 0 505 OAFBRx 3 OARRIP 0 0 619 0 625 0 631 OAFBRx 4 OARRIP 0 N...

Page 55: ...he settling time of the amplifier itself might be faster Operational Amplifier OA Feedback Network Inverting Amplifier Mode OAFCx 6 MSP430F22x4 Only 1 over recommended ranges of supply voltage and ope...

Page 56: ...r first byte or word 2 25 tFTG Block program time for each additional tBlock 1 63 2 18 tFTG byte or word tBlock End Block program end sequence wait time 2 6 tFTG tMass Erase Mass erase time 2 10593 tF...

Page 57: ...tance on TEST 2 2 V 3 V 25 60 90 k 1 Tools accessing the Spy Bi Wire interface need to wait for the maximum tSBW En time after pulling the TEST SBWCLK pin high before applying the first SBWCLK clock e...

Page 58: ...ATION Port P1 Pin Schematic P1 0 to P1 3 Input Output With Schmitt Trigger Table 21 Port P1 P1 0 to P1 3 Pin Functions CONTROL BITS SIGNALS PIN NAME P1 x x FUNCTION P1DIR x P1SEL x P1 0 1 I 0 O 1 0 P1...

Page 59: ...P1 Pin Schematic P1 4 to P1 6 Input Output With Schmitt Trigger and In System Access Features Table 22 Port P1 P1 4 to P1 6 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P1 x x FUNCTION P1DIR x P1SEL...

Page 60: ...0F22x2 MSP430F22x4 SLAS504G JULY 2006 REVISED AUGUST 2012 www ti com Port P1 Pin Schematic P1 7 Input Output With Schmitt Trigger and In System Access Features Table 23 Port P1 P1 7 Pin Functions CONT...

Page 61: ...2 Input Output With Schmitt Trigger Table 24 Port P2 P2 0 P2 2 Pin Functions CONTROL BITS SIGNALS 1 Pin Name P2 x x y FUNCTION P2DIR x P2SEL x ADC10AE0 y P2 0 2 I O I 0 O 1 0 0 P2 0 ACLK A0 OA0I0 0 0...

Page 62: ...LAS504G JULY 2006 REVISED AUGUST 2012 www ti com Port P2 Pin Schematic P2 1 Input Output With Schmitt Trigger Table 25 Port P2 P2 1 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P2 x x y FUNCTION P2DI...

Page 63: ...DVCC P2REN 3 ADC10AE0 3 Pad Logic INCHx 3 To ADC10 1 OA1 1 OAFCx OAPMx OAADCx To OA1 Feedback Network To ADC10 VR 1 0 SREF2 VSS P2 3 TA1 A3 VREF VeREF OA1I1 OA1O 1 OAADCx 10 or OAFCx 000 and OAPMx 00...

Page 64: ...3 2 I O I 0 O 1 0 0 Timer_A3 CCI1B 0 1 0 P2 3 TA1 A3 VREF 3 3 VeREF OA1I1 OA1O Timer_A3 TA1 1 1 0 A3 VREF VeREF OA1I1 OA1O 3 X X 1 1 X Don t care 2 Default after reset PUC POR 3 Setting the ADC10AE0...

Page 65: ...006 REVISED AUGUST 2012 Port P2 Pin Schematic P2 4 Input Output With Schmitt Trigger Table 27 Port P2 P2 4 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P2 x x y FUNCTION P2DIR x P2SEL x ADC10AE0 y P2...

Page 66: ...F22x4 SLAS504G JULY 2006 REVISED AUGUST 2012 www ti com Port P2 Pin Schematic P2 5 Input Output With Schmitt Trigger and External ROSC for DCO Table 28 Port P2 P2 5 Pin Functions CONTROL BITS SIGNALS...

Page 67: ...ator BCSCTL3 LFXT1Sx 11 P2 7 XOUT 0 1 1 LFXT1CLK MSP430F22x2 MSP430F22x4 www ti com SLAS504G JULY 2006 REVISED AUGUST 2012 Port P2 Pin Schematic P2 6 Input Output With Schmitt Trigger and Crystal Osci...

Page 68: ...AS504G JULY 2006 REVISED AUGUST 2012 www ti com Port P2 Pin Schematic P2 7 Input Output With Schmitt Trigger and Crystal Oscillator Output Table 30 Port P2 P2 7 Pin Functions CONTROL BITS SIGNALS 1 PI...

Page 69: ...E P1 x x y FUNCTION P3DIR x P3SEL x ADC10AE0 y P3 0 2 I O I 0 O 1 0 0 P3 0 UCB0STE 0 5 UCB0STE UCA0CLK 3 4 X 1 0 UCA0CLK A5 A5 5 X X 1 1 X Don t care 2 Default after reset PUC POR 3 The pin direction...

Page 70: ...x x FUNCTION P3DIR x P3SEL x P3 1 2 I O I 0 O 1 0 P3 1 UCB0SIMO UCB0SDA 1 UCB0SIMO UCB0SDA 3 X 1 P3 2 2 I O I 0 O 1 0 P3 2 UCB0SOMI UCB0SCL 2 UCB0SOMI UCB0SCL 3 X 1 P3 3 2 I O I 0 O 1 0 P3 3 UCB0CLK...

Page 71: ...put Output With Schmitt Trigger Table 33 Port P3 P3 6 P3 7 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P3 x x y FUNCTION P3DIR x P3SEL x ADC10AE0 y P3 6 2 I O I 0 O 1 0 0 P3 6 A6 OA0I2 6 6 A6 OA0I2...

Page 72: ...REVISED AUGUST 2012 www ti com Port P4 Pin Schematic P4 0 to P4 2 Input Output With Schmitt Trigger Table 34 Port P4 P4 0 to P4 2 Pin Functions CONTROL BITS SIGNALS PIN NAME P4 x x FUNCTION P4DIR x P4...

Page 73: ...P4DIR 6 P4SEL 6 ADC10AE1 7 P4 6 TBOUTH A15 OA1I3 Timer_B Output Tristate Logic MSP430F22x2 MSP430F22x4 www ti com SLAS504G JULY 2006 REVISED AUGUST 2012 Port P4 Pin Schematic P4 3 to P4 4 Input Output...

Page 74: ...CI0B 0 1 0 P4 3 TB0 A12 OA0O 3 4 Timer_B3 TB0 1 1 0 A12 OA0O 3 X X 1 P4 4 2 I O I 0 O 1 0 0 Timer_B3 CCI1B 0 1 0 P4 4 TB1 A13 OA1O 4 5 Timer_B3 TB1 1 1 0 A13 OA1O 3 X X 1 1 X Don t care 2 Default afte...

Page 75: ...VISED AUGUST 2012 Port P4 Pin Schematic P4 5 Input Output With Schmitt Trigger Table 36 Port P4 P4 5 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P4 x x y FUNCTION P4DIR x P4SEL x ADC10AE1 y P4 5 2 I...

Page 76: ...6 Input Output With Schmitt Trigger Table 37 Port P4 P4 6 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P4 x x y FUNCTION P4DIR x P4SEL x ADC10AE1 y P4 6 2 I O I 0 O 1 0 0 TBOUTH 0 1 0 P4 6 TBOUTH A1...

Page 77: ...x2 MSP430F22x4 www ti com SLAS504G JULY 2006 REVISED AUGUST 2012 Port P4 Pin Schematic P4 7 Input Output With Schmitt Trigger Table 38 Port P4 Pr 7 Pin Functions CONTROL BITS SIGNALS PIN NAME P4 x x F...

Page 78: ...currents are terminated Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up The second positive edge on the...

Page 79: ...ames in Port P3 pin schematic P3 1 to P3 5 and Port P3 P3 1 to P3 5 pin functions page 69 Corrected signal names in Port P2 pin schematic P2 5 input output page 65 D1 Corrected values in x column in P...

Page 80: ...CU NIPDAU Level 2 260C 1 YEAR 40 to 105 M430F2232T MSP430F2232TDAR ACTIVE TSSOP DA 38 2000 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 105 M430F2232T MSP430F2232TRHAR ACTIVE VQFN RHA 40 2...

Page 81: ...0 F2252 MSP430F2252IYFFR ACTIVE DSBGA YFF 49 2500 Green RoHS no Sb Br SNAGCU Level 1 260C UNLIM M430F2252 MSP430F2252IYFFT ACTIVE DSBGA YFF 49 250 Green RoHS no Sb Br SNAGCU Level 1 260C UNLIM M430F22...

Page 82: ...F2272IRHAR ACTIVE VQFN RHA 40 2500 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 M430 F2272 MSP430F2272IRHAT ACTIVE VQFN RHA 40 250 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to...

Page 83: ...Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS no Sb Br please check http www ti com productcontent for the latest availability information and additional...

Page 84: ...aken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals T...

Page 85: ...0 16 0 Q2 MSP430F2234IRHAT VQFN RHA 40 250 180 0 16 4 6 3 6 3 1 1 12 0 16 0 Q2 MSP430F2234TRHAR VQFN RHA 40 2500 330 0 16 4 6 3 6 3 1 1 12 0 16 0 Q2 MSP430F2252IDAR TSSOP DA 38 2000 330 0 24 4 8 6 13...

Page 86: ...8 6 13 0 1 8 12 0 24 0 Q1 MSP430F2274IRHAR VQFN RHA 40 2500 330 0 16 4 6 3 6 3 1 1 12 0 16 0 Q2 MSP430F2274IRHAT VQFN RHA 40 250 180 0 16 4 6 3 6 3 1 1 12 0 16 0 Q2 MSP430F2274TRHAR VQFN RHA 40 2500...

Page 87: ...40 2500 367 0 367 0 38 0 MSP430F2254IRHAT VQFN RHA 40 250 210 0 185 0 35 0 MSP430F2254TRHAR VQFN RHA 40 2500 367 0 367 0 38 0 MSP430F2254TRHAT VQFN RHA 40 250 210 0 185 0 35 0 MSP430F2272IDAR TSSOP DA...

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Page 93: ...D Max E Max 3 518 mm Min 3 36 mm Min 3 458 mm 3 3 mm...

Page 94: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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