Texas Instruments MMWCAS-DSP-EVM, User Manual, Page: 17 / 20

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Hardware Specifications
17 SPRUIS6 – September 2019
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MMWCAS-DSP-EVM
2.5.6 JTAG and Emulator (J19)
The EVM has support of the following JTAG emulation headers:
• 60-pin MIPI Connector
• Standard 14-pin to 60-pin MIPI adapter
• 20-pin CTI to 60-pin MIPI adapter
2.5.7 Lattice ECP5 FPGA Prototyping Header (J20)
Included on the EVM is a Lattice Prototyping connector. The interface brings out the VOUT1 interface,
I2C5, and two I2C GPIO expander pins to allow for interfacing to a separate Lattice ECP5 FPGA card,
which performs VOUT to 10GBase-KR bridging.
2.6 GPIO, Switches, Push Buttons, and LEDs
2.6.1 GPIO List
The MMWCAS-DSP-EVM supports a number of GPIOs, some of which can be user controlled. Table 4
shows the GPIO list.
Table 4. GPIO List and Description
GPIO for EVM Function/Description
TDA_GPIO1_15_ALERT# PCIe SSD Alert notification to master. Active Low. Open-Drain with pullup on board. '0' -
Active '1' - Inactive(Default)
GPIO_EXP_P13(PERST#) PCIe Reset - functional reset to the card '0' - Hold in reset until stable(Default) '1' - Release
from reset
GPIO_EXP_P14(CLKREQ#) PCIe Reference Clock Request '0' - Request for clock '1' - Not Active(Default)
GPIO6_8 Selects between AWR and FPGA/Flash for SPI1 '0' - Selects AWR(Default) '1' - Selects
FPGA/Flash
GPIO6_6 When ganged. Controls FPGA1/2/3/4 CRESETN signals '0' - Holds FPGA in Reset(Default)
'1' - released FPGA from Reset
GPIO7_31 Controls FPGA1 CRESETN signals '0' - Holds FPGA1 in Reset(Default) '1' - released
FPGA1 from Reset
GPIO7_30 Controls FPGA2 CRESETN signals '0' - Holds FPGA2 in Reset(Default) '1' - released
FPGA2 from Reset
GPIO5_13 Controls FPGA3 CRESETN signals '0' - Holds FPGA3 in Reset(Default) '1' - released
FPGA3 from Reset
GPIO5_14 Controls FPGA4 CRESETN signals '0' - Holds FPGA4 in Reset(Default) '1' - released
FPGA4 from Reset
GPIO1_14 Control FPGA1/2/3/4 Flash RESETn Signals '0' - Hold in Reset '1' - Release from Reset
(Default)
GPIO7_27 AWR Extern SYNC
SMB_CLK SMBus Clock. I2C1 SCL for PCIe
SMB_DATA SMBus Data. I2C1 SDA for PCIe
I2C1 SCL EEPROM(U100) Serial Clock Address: 0x50
I2C1 SDA EEPROM(U100) Serial Data Address: 0x50