Texas Instruments M-LVDS User Manual Download Page 7

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Running Title—Attribute Reference

vii

Chapter Title—Attribute Reference

Contents

The M-LVDS Evaluation Module

1-1

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1.1

Overview

1-2

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1.2

M-LVDS Standard TIA/EIA−899

1-3

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1.3

M-LVDS EVM Kit Contents

1-4

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1.4

Configurations

1-5

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1.4.1

Point-to-Point

1-5

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1.4.2

Multidrop

1-6

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1.4.3

Multipoint

1-6

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1.4.4

EVM Operation With Separate Power Supplies

1-7

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1.5

Recommended Equipment

1-8

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Test Setup

2-1

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2.1

Typical Cable Test Configurations

2-2

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2.1.1

Point-to-Point Simplex Transmission

2-2

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2.1.2

Point-to-Point Parallel Terminated Simplex Transmission

2-3

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2.1.3

Two-Node Multipoint Transmission

2-3

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2.2

Test Results

2-5

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Bill of Materials, Board Layout, and PCB Construction

3-1

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3.1

Bill of Materials

3-2

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3.2

Board Layout

3-3

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3.3

PCB Construction

3-6

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Schematic

A-1

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Summary of Contents for M-LVDS

Page 1: ...Multipoint Low Voltage Differential Signaling M LVDS Evaluation Module April 2004 High Performance Analog User s Guide SLLU039B ...

Page 2: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

Page 3: ... handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR A...

Page 4: ...inty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 125 C The EVM is designed to operate properly with certain components above 125 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transist...

Page 5: ...4 SN65MLVD20x data sheets Multipoint LVDS Line Drivers and Receivers SLLS573 and SLLS558 Electromagnetic Compatibility Printed Circuit Board and Electronic Module Design VEC workshop Violette Engineering Corporation FCC Warning This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance wit...

Page 6: ...vi ...

Page 7: ...ultipoint 1 6 1 4 4 EVM Operation With Separate Power Supplies 1 7 1 5 Recommended Equipment 1 8 2 Test Setup 2 1 2 1 Typical Cable Test Configurations 2 2 2 1 1 Point to Point Simplex Transmission 2 2 2 1 2 Point to Point Parallel Terminated Simplex Transmission 2 3 2 1 3 Two Node Multipoint Transmission 2 3 2 2 Test Results 2 5 3 Bill of Materials Board Layout and PCB Construction 3 1 3 1 Bill o...

Page 8: ...implex Transmission 2 2 2 2 Point to Point Parallel Terminated Simplex Transmission 2 3 2 3 Two Node Multipoint Transmission 2 4 2 4 Point to Point Parallel Simplex Typical Eye Pattern Data 2 5 2 5 Parallel Terminated Point to Point Parallel Simplex Typical Eye Pattern Data 2 6 2 6 Two Node Multipoint Typical Eye Pattern Data 2 6 3 1 Assembly Drawing 3 3 3 2 Top Layer 3 3 3 3 Second Layer 3 4 3 4 ...

Page 9: ...leased devices referred to in Table 1 1 Using the EVM to evaluate these devices should provide insight into the design of low voltage differential circuits The EVM board allows the designer to connect an input to one or both of the drivers and configure a point to point multidrop or multipoint data bus The EVM can be used to evaluate device parameters while acting as a guide for high frequency boa...

Page 10: ...of the unit interval UI The definition of transition time tr and tf in M LVDS is the 10 to 90 levels shown in Figure 1 1 Using the maximum transition time for each of the drivers and the 0 5 tUI rule results in the signaling rates shown in Table 1 1 This slew rate control differentiates M LVDS devices from LVDS TIA EIA 644A compliant devices The slower transition times available with M LVDS help t...

Page 11: ...rchitectures therefore the need for development of a new standard The standard Electrical Characteristics of Multipoint Low Voltage Differential Signaling M LVDS TIA EIA 899 specifies low voltage differential signaling drivers and receivers for data interchange across half duplex or multipoint data bus structures M LVDS is capable of operating at signaling rates up to 500 Mbps In other words when ...

Page 12: ...ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Low High Low High Transition Region Type 1 and Type 2 Receiver Differential Input Thresholds Type 1 Type 2 2 4 2 4 1 3 M LVDS EVM Kit Contents The M LVDS EVM kit contains the following J M LVDS EVM PWB with SN65MLVD201D and SN65MLVD207D installed 6424409B J Additional devices SN65MLVD200A SN65MLVD202A S...

Page 13: ...wn in Figure 2 1 Although this is not the intended mode of operation for M LVDS it works well for high noise or long higher loss transmission lines Due to the increased drive current a single 100 Ω termination resistor on the EVM will result in a differential bus voltage VOD twice as large as a doubly terminated line This practice is acceptable as long as the combination of input voltage and commo...

Page 14: ...dard compliant TIA EIA 644A receivers on the bus in addition to M LVDS receivers Figure 1 5 Multidrop or Distributed Simplex Circuit T 1 4 3 Multipoint The multipoint configuration is the primary application of the M LVDS devices and the associated standard The M LVDS standard allows for any combination of drivers receivers or transceivers up to a total of 32 on the line Figure 1 6 shows a represe...

Page 15: ...care should be taken to ensure the absolute maximum device ratings are not exceeded Keep in mind that if jumpers W7 8 9 and 10 are not removed when using separate power supplies a difference in potential between the supplies causes a current to flow between supplies and through the jumpers The EVM can be configured with three power supplies with isolated outputs in such a way as to input a fixed o...

Page 16: ...dc at 0 5 A power supply or multiple power supplies with both devices powered and enabled the board draws about 35 mA A 100 Ω transmission medium from the driver to the receiver twisted pair cable recommended CAT5 cable for example A function or pattern generator capable of supplying 3 3 V signals at the desired signaling rate A multiple channel high bandwidth oscilloscope preferably above the 1 G...

Page 17: ...2 1 Test Setup Test Setup This chapter describes how to setup and use the M LVDS EVM Topic Page 2 1 Typical Cable Test Configurations 2 2 2 2 Test Results 2 5 Chapter 2 ...

Page 18: ... 6 7 Figure 2 1 Point to point parallel terminated simplex transmission W1 2 7 8 9 10 R4 7 R5 6 Figure 2 2 Two node multipoint transmission W1 2 3 4 7 8 9 10 R5 16 R2 4 6 7 13 15 Figure 2 3 2 1 1 Point to Point Simplex Transmission 1 Connect a twisted pair cable from P1 to P2 2 Verify resistor R4 is installed 3 Remove resistors R5 R6 and R7 This properly terminates the transmission line at one end...

Page 19: ...be into one Channel of Scope Terminated in High Impedance Cable Active Voltage Probe 50 Ω 50 Ω 50 cable or Ω with 50 Ω 2 1 3 Two Node Multipoint Transmission 1 Connect a twisted pair cable between P1 P2 and P3 2 Verify resistor R5 and R16 are installed 3 Remove resistors R4 R6 R7 and R15 This properly terminates the transmission line at both ends 4 Enabling the driver in a two node multipoint conf...

Page 20: ...nput Signal R13 453 J7 TP3 R2 453 J1 Output Signal TP1 TP4 3 W1 VCC Jumper 1 3 W4 VCC Jumper 2 W3 Jumper VCC W2 VCC Jumper 4 TP2 P1 Signal Source Output Cable Active Voltage Probe into one Channel of Scope Terminated in High Impedance Cable Output Signal Cable Active Voltage Probe Active Voltage Probe Active Voltage Probe into one Channel of Scope Terminated in High Impedance 50 Ω 50 cable or Ω wi...

Page 21: ...ceiver output in both figures shows the offset zero crossing which is due to the Type 2 receiver incorporated into the SN65MLVD207 device The reduced offset from a Type 1 receiver can be seen in Figure 2 6 receiver number 2 output Measuring the output signal on J1 with a 50 Ω cable terminated into 50 Ω at the scope will attenuate the signal due to the 453 Ω resistor in series with the receiver out...

Page 22: ... Point Parallel Simplex Typical Eye Pattern Data Driver Input Receiver Output Differential Bus Voltage Figure 2 6 represents the two node multipoint transmission eye patterns where trace 1 is the input signal applied to J2 and traces 2 and 3 are the output signals seen at TP1 and TP3 respectively with R2 and R13 shorted The offset zero crossing shows the difference between Type 2 Receiver 1 Output...

Page 23: ... Bill of Materials Board Layout and PCB Construction This chapter contains the bill of materials board layout of the M LVDS and describes the printed circuit board Topic Page 2 1 Bill of Materials 3 2 3 2 Board Layout 3 3 3 3 PCB Construction 3 6 Chapter 3 ...

Page 24: ...MP 4 103239 0x2 8 3 P1 P3 Header make from 4 103239 0 AMP 4 103239 0x2 9 4 W7 W10 Header make from 4 103239 0 AMP 4 103239 0x2 10 4 W1 W4 Header make from 4 103239 0 AMP 4 103239 0x3 11 1 U1 IC SMT 14P High speed 50 Ω line driver receiver TI SN65MLVD202AD SN65MLVD205AD SN65MLVD203D SN65MLVD207D 12 1 U2 IC SMT 8P High speed 50 Ω line driver receiver TI SN65MLVD200AD SN65MLVD204AD SN65MLVD201D SN65M...

Page 25: ...ENTS A W NO 6424409B PWA EVM SN65MLVD SERIAL NO MADE IN U S A GND VCC VCC01 GND01 GND01 VCC01 GND VCC U1 J10 J9 J8 J7 J6 J4 J3 J2 J1 J17 J15 J13 J11 J18 J16 J14 J12 R14 R12 R3 R1 R13 R2 W4 W3 W2 W1 W10 W9 W8 W7 TP4 TP3 TP1 P3 P2 P1 TP2 R16 R15 R7 R6 R5 R4 R18 R17 R11 R8 R9 J5 R10 U2 The top layer of the EVM contains the controlled impedance and matched length traces Figure 3 2 Top Layer ...

Page 27: ...oard Layout and PCB Construction The bottom layer of the EVM contains bulk and decoupling capacitors to be placed close to the power and ground pins on the device Figure 3 5 Bottom Layer C9 C8 C7 C5 C4 C3 C10 C6 C2 C1 VCC GND VCC01 GND01 ...

Page 28: ...ated by ZO 60 0 475år 0 67 Ǹ ln 4h 0 67 0 8 W t 1 where εr is the permeability of the board material h is the distance between the ground plane and the signal trace W is the trace width and t is the thickness of the trace The differential impedance for a two microstrip traces can be approximated as follows with S being the distance between two microstrip traces ZDIFF 2 ZO ǒ1 0 48e 0 96sńhǓ 2 Strip...

Page 29: ...es close Other factors to keep in mind when doing a printed circuit layout for transmission lines are as follows 1 Differences in electrical length translate into skew 2 Careful attention to dimensions length and spacing help to insure isola tion between differential pairs 3 Where possible use ideal interconnects point to point with no loads or branches This keeps the impedance more uniform from e...

Page 30: ...ip construction Table 3 2 EVM Layer Stack Up Differential Model Single Ended Model Material Type FR 406 Layer No Layer Type Thickness mils Copper Weight Line Width mils Spacing mils Impedance Ω Line Width mils Impedance Ω 1 Signal 0 0006 0 5 oz start 0 027 0 230 100 0 0420 50 PREPREG 0 025 2 Plane 0 0012 1 CORE 0 004 3 Plane 0 0012 1 PREPREG 0 025 4 Signal 0 0006 0 5 oz start 0 027 0 230 100 0 042...

Page 31: ...A 1 Schematic Schematic This Appendix contains the EVM schematic Appendix A ...

Page 32: ...8 D 5 GND 5 R 2 RE 3 NC 1 Y 9 NC 8 DE 4 GND 7 Z 10 B 11 A 12 Vcc 13 Vcc 14 U1 SN65M LVD202 203 205 OR 207 DE 3 D 4 GND 5 A 6 B 7 Vcc 8 RE 2 R 1 U2 SN65M LVD200 201 204 OR 206 TP1 P1 R5 100 R7 100 P2 R6 100 R15 100 P3 R16 100 R17 0 0 R18 0 0 R10 0 0 R11 0 0 R8 0 0 R9 0 0 J 10 J 9 J 6 J 5 J 4 J 3 R1 49 9 R2 453 R13 453 R14 49 9 R3 49 9 TP3 R12 49 9 TP2 TP4 C10 1 0uF C8 10uF C9 1uF Vcc VCC VCC01 W 10...

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