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9
1
0
1
1
1
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1
3
1
4
2
5
2
6
2
7
2
8
24
23
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21
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19
18
17
F
AU
L
T
SQW
OUT4
IF
C1P
C1N
C
PU
MP
VDD
SD
O
U
T
1
OUT2
LGND
F
B
SG
N
D
F
IL
T
ER
ISET
TSENSE
SYN
C
VSYN
C
PWM
MI
SO
NSS
OUT3
1
5
1
6
2
9
3
0
3
1
3
2
PG
N
D
G
D
ISEN
SE
ISEN
SE
_
G
N
D
VDDIO/EN
SC
L
K
/SC
L
MO
SI
/SD
A
VSENSE_P
VSENSE_N
VDD
BATTERY
+VBATT
-VBATT
VIA to GND plane
Input capacitors
D1
C8
C9
C3
C4
R1
R2
Q1
L1
Q2
R3
R5
C5
C1
C2
R4
C7
C6
Ground wire for
current sensor
Output capacitors
Feedback line
Connection
between PGND
and GND
LP8860-Q1
ISENSE
FB
SGND
PWM
OUT1
OUT2
OUT3
OUT4
L1
D1
+VBATT
FILTER
VSYNC
SD
GD
VSENSE_N
Q2
ISENSE_GND
CPUMP
C1P
C1N
VDD
SYNC
VDDIO/EN
SCLK/SCL
MOSI/SDA
MISO
NSS
PGND LGND
PAD
IF
VSENSE_P
R1
TSENSE
ISET
FAULT
SQW
VDD 3.3V
Q1
R2
C1
C2
C3
C4
C5
R3
R4
R5
C6
C7
C8
C9
2
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6
3
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14
SNVU382A – April 2014 – Revised June 2014
Copyright © 2014, Texas Instruments Incorporated
Board Layout
Figure 4-3. PCB Layout Example
See the
for PCB layout guidelines.