Texas Instruments LP87745-Q1, User Manual

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5 Watchdog
This section provides the basic overview of the SPI based Q&A watchdog algorithm implemented on the EVM.
Please refer LP87745-Q1 device data sheet for more detailed information about device watchdog functionality.
This watchdog requires specific SPI messages from the host MCU in specific time intervals to detect correct
operation of the MCU. On the EVM, MSP432 MCU is used as a host MCU.
During operation, the device provides a 4-bit question for the MCU and the MCU calculates the required 32-bit
answer. This answer is split into four answer bytes: Answer-3, Answer-2, Answer-1 and Answer-0. The MCU
writes these answer bytes one byte at a time into WD_ANSWER[7:0] from the SPI interface.
A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the
correct watchdog window and in the correct sequence. This sequence is visualized in
Figure 5-1
A bad event occurs when one of the events that follows occur:
• The MCU sends the correct answer-bytes, but not in the correct watchdog window.
• The MCU sends incorrect answer-bytes.
• The MCU returns correct answer-bytes, but in the incorrect sequence.
Window-2 Window-1
Three correct answer-bytes must be provided in Window-1 and
in the correct order:
x
Answer-3
x
Answer-2
x
Answer-1
After the Window-1 time elapses, Window 2 begins.
The MCU needs to write the answer-bytes to the WD_ANSWER[7:0] bits.
The fourth answer-byte, Answer-0, must be provided
in Window-2.
After the MCU writes the fourth Answer-0 to
WD_ANSWER[7:0], the Watchdog generates the
next question within 1 Internal System Clock Cycle,
after which the next Watchdog Sequence
(Q&A [n + 1]) begins
Write to
WD_ANSWER[7:0]
-> Answer-3
MCU provides answer
(2)
Answer
Read bits WD_
QUESTION[3:0]
MCU reads question
(1)
I2C2 / SPI
Commands
NCS Pin (for
SPI only)
1 Internal System Clock Cycle
to Generate a new question for the next watchdog
sequence Q&A [n + 1]
Q&A [n] Q&A [n + 1]
Question
Watchdog Sequence
Write to
WD_ANSWER[7:0]
-> Answer-1
Write to
WD_ANSWER[7:0]
-> Answer-0
t = t
WINDOW-1
t = t
WINDOW-2
Write to
WD_ANSWER[7:0]
-> Answer-2
Figure 5-1. Watchdog Sequence in Q&A Mode
In GUI, there are two sections in configuration tab for watchdog configurability. Figure 5-2 illustrates the
watchdog validation section in GUI, where the delays between the WD Answers can be configured and
watchdog status for different interrupts and errors can be observed. And if required status can be cleared
through clear buttons available next to the each status. In the other watchdog configuration section, watchdog
can be enabled or disabled along with other watchdog configurable parameters as shown in
Figure 5-3 . For
further information on watchdog configuration, refer to the data sheet of LP8774x-Q1 SNVSBE7 for watchdog
section.
Watchdog www.ti.com
12 LP877451Q1EVM Evaluation Module SNVU769A – SEPTEMBER 2021 – REVISED OCTOBER 2022
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