8 Schematic
illustrates the EVM schematic.
GND
VDD
0.1µF
C3
10V
C2
GND
VDD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
100
R1
100
R3
GND
VDD
1
2
3
J3
GND
VDD
0
R4
0
R9
100
R5
100
R17
VDD
GND
Y0
Y0
0
R25
100
R21
100
R33
VDD
GND
Y1
0
R11
100
R6
100
R18
VDD
GND
Y2
Y2
0
R27
100
R22
100
R34
VDD
GND
Y3
Y3
0
R15
100
R8
100
R20
VDD
GND
Y6
Y6
0
R13
100
R7
100
R19
VDD
GND
Y4
Y4
0
R29
100
R23
100
R35
VDD
GND
Y5
Y5
0
R31
100
R24
100
R36
VDD
GND
Y7
Y7
GND
GND
GND
GND
GND
GND
GND
GND
5pF
C6
5pF
C10
5pF
C7
5pF
C11
5pF
C8
5pF
C12
5pF
C9
5pF
C13
L1
TP1
0.1µF
C4
0.1µF
C5
0
R10
0
R26
0
R12
0
R28
0
R30
0
R14
0
R16
0
R32
Put C3, C4, C5 next to VDD Pins
Put L1, C1, C2, TP1 close to Terminal
block connector
Put these components close to SMA
connector
Put R9 close to the output pin of
device, and every thing else close to
SMA connector
Put R25 close to the output pin of
device, and every thing else close to
SMA connector
Put R11 close to the output pin of
device, and every thing else close to
SMA connector
Put R27 close to the output pin of
device, and every thing else close to
SMA connector
Put R13 close to the output pin of
device, and every thing else close to
SMA connector
Put R29 close to the output pin of
device, and every thing else close to
SMA connector
Put R15 close to the output pin of
device, and every thing else close to
SMA connector
Put R31 close to the output pin of
device, and every thing else close to
SMA connector
GND
0
R2
CLKIN
1G
TP2
GND
Y1
VDD = 1.8V / 2.5V / 3.3V @
300mA (max)
1
2 3 4 5
J2
1
2
3
4
5
J4
1
2
3
4
5
J5
1
2
3
4
5
J6
1
2
3
4
5
J7
1
2
3
4
5
J8
1
2
3
4
5
J9
1
2
3
4
5
J10
1
2
3
4
5
J11
CLKIN
1
1G
2
Y0
3
GND
4
VDD
5
Y4
6
GND
7
VDD
10
Y5
11
GND 12
Y2
13
VDD
14
Y3
15
Y1
16
Y6
8
Y7
9
LMK1C1108PW
U1
1
2
J1
GND
10V
10uF
C1
Figure 8-1. LMK1C1108 Schematic
Schematic
SNAU262A – DECEMBER 2020 – REVISED JANUARY 2021
LMK1C1108 Low-Additive, Phase-Noise LVCMOS Clock Buffer Evaluation Board
5
Copyright © 2021 Texas Instruments Incorporated