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5 Enabling and Disabling the Outputs
The enable pin, 1G, of the LMK1C1108 can be controlled using jumper
J3
. Pull 1G to VDD by shunting pins 2
and 3 of J3 to enable the outputs as shown in
. Leave 1G floating or pull to GND to disable the
outputs.
J3:
Shunt pins 2 (1G) and
3 (VDD) to enable the
outputs
Figure 5-1. J3 Jumper Location
By default, a shunt is placed on pins 2 and 3 to enable the outputs.
6 Output Clock
The LMK1C1108 fans out eight LVCMOS outputs. The outputs can be loaded using the pullup and pulldown
footprints. The resistors have been soldered in those footprints.
Enabling and Disabling the Outputs
SNAU262A – DECEMBER 2020 – REVISED JANUARY 2021
LMK1C1108 Low-Additive, Phase-Noise LVCMOS Clock Buffer Evaluation
Board
3
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