ADV
ANCEINFORMA
TION
LMK05028
HCSL
Driver
HCSL
50
50
Copyright © 2018, Texas Instruments Incorporated
24
SNAS724 – FEBRUARY 2018
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Copyright © 2018, Texas Instruments Incorporated
Figure 24. Interfacing LMK05028 Inputs With HCSL Driver (Load Terminated)
9.3.4 Reference Input Mux Selection
For each DPLL, the reference input mux selection can be done automatically using an internal state machine
with a configurable input priority scheme manually through register control or hardware pin controls. The input
mux can select from IN0 to IN3. Additionally, DPLL1 can select IN5 as an internal loopback clock divided from
PLL2 VCO (VCO2), and DPLL2 can select IN4 as an internal loopback clock from PLL1 VCO (VCO2).
The priority for all inputs can be assigned for each DPLL through registers. The priority ranges from 0 to 6, where
0 means Ignored (never select) and 1 to 6 are highest (1st) to lowest (6th) priority. When two or more inputs are
configured with the same priority setting, the reference input with lower index (INx) will be given higher priority.
The currently selected reference input for each DPLL can be read through a status pin or register.
9.3.4.1 Automatic Input Selection
There are two automatic input selection modes that can be set by a register: Auto Revertive and Auto Non-
Revertive.
•
Auto Revertive:
In this mode, the DPLL automatically selects the valid input with the highest configured
priority. If a clock with higher priority becomes valid, the DPLL will automatically switch over to that clock
immediately.
•
Auto Non-Revertive:
In this mode, the DPLL automatically selects the highest priority input that is valid. If a
higher priority input because valid, the DPLL will not switch-over until the currently selected input becomes
invalid.
9.3.4.2 Manual Input Selection
There are two manual input selection modes that can be set by a register: Manual with Auto-Fallback and
Manual with Auto-Holdover. In either manual mode, the input selection can be done through register control
(
) or hardware pin control (
•
Manual with Auto-Fallback:
In this mode, the manually selected reference is the active reference until it
becomes invalid. If the reference becomes invalid, the DPLL will automatically fallback to the highest priority
input that is valid or qualified. If no prioritized inputs are valid, the DPLL will enter holdover mode (if tuning
word history is valid) or free-run mode. The DPLL will exit holdover mode when the selected input becomes
valid.
•
Manual with Auto-Holdover:
In this mode, the manually selected reference is the active reference until it
becomes invalid. If the reference becomes invalid, the DPLL will automatically enter holdover mode (if tuning
word history is valid) or free-run mode. The DPLL will exit holdover mode when the selected input becomes
valid.
Table 4. Manual Input Selection by Register Bits
DPLLx_REF_MAN_REG_SEL[2
:0] BITS
DPLLx_REF_MAN_SEL BIT
SELECTED INPUT
00b
0
IN0
Summary of Contents for LMK05028
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