manualshive.com logo in svg

Texas Instruments LMK04906 Series, User Manual

Share
Download
Texas Instruments LMK04906 Series User Manual Download Page 14

 

 

14

     

SNAU126A

 

LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs 

           Revised - December 2013

 

Copyright © 2013, Texas Instruments Incorporated

 

Evaluation Board Inputs and Outputs 

The following table contains descriptions of the inputs and outputs for the evaluation board.  
Unless otherwise noted, the connectors described can be assumed to be populated by default.  
Additionally, some applicable CodeLoader programming controls are noted for convenience.  
Refer to the 

LMK04906 Family Datasheet

 for complete register programming information. 

 

Table 6: Evaluation Board Inputs and Outputs 

Connector Name 

Signal Type, 

Input/Output 

Description 

Populated: 

CLKout0, CLKout0*,  
CLKout1, CLKout1*, 
CLKout2, CLKout2*, 
CLKout3, CLKout3*,  
CLKout4, CLKout4*, 

CLKout5, CLKout5* 

 
 

Analog,  Output 

Clock outputs with programmable output buffers. 
 
The output terminations by default on the evaluation board 
are shown below, and the output type selected by default in 
CodeLoader is indicated by an asterisk (*): 
 

Clock output pair 

Default Board Termination 

CLKout0 

LVPECL* 

CLKout1 

LVPECL 

CLKout2 

LVDS* / LVCMOS 

CLKout3 

LVDS / LVCMOS 

CLKout4 

LVDS* / LVCMOS 

CLKout5 

LVPECL 

 
Each CLKout pair has a programmable LVDS, LVPECL, or 
LVCMOS buffer.  The output buffer type can be selected in 
CodeLoader in the 

Clock Outputs

 tab via the 

CLKoutX_TYPE control. 
 
All clock outputs are AC-coupled to allow safe testing with 
RF test equipment. 
 
All LVPECL

 

clock outputs are source-terminated using 240-

ohm resistors.   
 
If an output pair is programmed to LVCMOS, each output 
can be independently configured (normal, inverted, or off/tri-
state).  

Summary of Contents for LMK04906 Series

Page 1: ...LMK04906 Evaluation Board User s Guide January 2012 Literature Number SNAU126A Revised December 2013 ...

Page 2: ...906 Family Low Noise Clock Jitter with Dual Loop PLLs Revised December 2013 Copyright 2013 Texas Instruments Incorporated LMK04906 Family Low Noise Clock Jitter Cleaner with Dual Loop PLLs Evaluation Board Instructions ...

Page 3: ...n 8 2 Select Device 8 3 Program Load Device 9 4 Restoring a Default Mode 9 5 Visual Confirmation of Frequency Lock 10 6 Enable Clock Outputs 10 PLL LOOP FILTERS AND LOOP PARAMETERS 12 PLL 1 Loop Filter 12 25 MHz VCXO PLL 12 PLL2 Loop Filter 13 EVALUATION BOARD INPUTS AND OUTPUTS 14 RECOMMENDED TEST EQUIPMENT 21 APPENDIX A CODELOADER USAGE 22 Port Setup Tab 22 Clock Outputs Tab 23 PLL1 Tab 26 Setti...

Page 4: ...42 APPENDIX D BILL OF MATERIALS 43 APPENDIX E PCB LAYERS STACKUP 47 APPENDIX F PCB LAYOUT 48 Layer 1 Top 48 Layer 2 RF Ground Plane Inverted 49 Layer 3 Vcc Planes 50 Layer 4 Ground Plane Inverted 51 Layer 5 Vcc Planes 2 52 Layer 6 Bottom 53 Layers 1 and 6 Top and Bottom Composite 54 APPENDIX G PROPERLY CONFIGURING LPT PORT 55 LPT Driver Loading 55 Correct LPT Port Address 55 Correct LPT Mode 56 Le...

Page 5: ... from Table 1 1 CodeLoader and USB2ANY uWIRE Interface uWire header on EVM Available LMK04906 Evaluation Boards The LMK04906 Evaluation Board supports any of the four devices offered in the LMK04906 Family All evaluation boards use the same PCB layout and bill of materials except for the corresponding LMK04906B device affixed to the board A commercial quality VCXO is also mounted to the board to p...

Page 6: ...y to operate the device 2 Connect a reference clock from a signal source to the CLKin1 SMA port Use 125 MHz for default The reference frequency depends on the device programming 3 Connect the uWire header to a PC USB port using the USB2ANY uWIRE interface 4 Program the device with a default mode using CodeLoader Ctrl L must be pressed at least once to load all registers Alternatively click menu Ke...

Page 7: ...LKin0 or CLKin2 for differential clock signal or CLKin1 for a single ended signal Figure 2 Selecting a Default Mode for the LMK04906 Device After restoring a default mode press Ctrl L to program the device The default modes also disable certain outputs so make sure to enable the output under test to make measurements Table 3 Default CodeLoader Modes for LMK04906 Default CodeLoader Mode Device Mode...

Page 8: ...i com tool codeloader Before proceeding be sure to follow the Quick Start section above to ensure proper connections 1 Start CodeLoader 4 Application Click Start Programs CodeLoader 4 CodeLoader 4 The CodeLoader 4 program is installed by default to the CodeLoader 4 application group 2 Select Device Click Select Device Clock Conditioners LMK04906B Once started CodeLoader 4 will load the last used d...

Page 9: ...n the next step this step is not really needed but is included to emphasize the importance of pressing Ctrl L to load the device at least once after starting CodeLoader restoring a mode or restoring a saved setup using the File menu See Appendix A CodeLoader Usage or the CodeLoader 4 instructions located at http www ti com tool codeloader for more information on Port Setup Appendix H Troubleshooti...

Page 10: ... needed a Digital Delay value b Clock Divider value c Analog Delay select and Analog Delay value if not Bypassed d Clock Output type 4 Depending on the configured output type the clock output SMAs can be interfaced to a test instrument with a single ended 50 ohm input as follows a For LVDS i A balun like ADT2 1T is recommended for differential to single ended conversion b For LVPECL i A balun can ...

Page 11: ...ed 5 The phase noise may be measured with a spectrum analyzer or signal source analyzer See Appendix B Typical Phase Noise Performance Plots for phase noise plots of the clock outputs National s Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies See http www ti com tool clockdesigntool ...

Page 12: ...en configured for a narrow loop bandwidth 100 Hz while the loop filter of PLL2 has been configured for a wide loop bandwidth 100 kHz The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board The following tables contain the parameters for PLL1 and PLL2 for each oscillator option National s Clock Design Tool can be used to optimize PLL phase noi...

Page 13: ...MK04906B C1_VCO 0 082 nF C2_VCO 5 6 nF C3 internal 0 01 nF C4 internal 0 01 nF R2_VCO 0 68 kΩ R3 internal 0 2 kΩ R4 internal 0 2 kΩ Charge Pump Current Kφ 3 2 mA Phase Detector Frequency 50 MHz Frequency 2500 MHz Kvco 18 5 MHz V N 50 Phase Margin 69 degree s Loop Bandwidth 132 kHz Note PLL Loop Bandwidth is a function of Kφ Kvco N as well as loop components Changing Kφ and N will change the loop b...

Page 14: ...CLKout2 CLKout2 CLKout3 CLKout3 CLKout4 CLKout4 CLKout5 CLKout5 Analog Output Clock outputs with programmable output buffers The output terminations by default on the evaluation board are shown below and the output type selected by default in CodeLoader is indicated by an asterisk Clock output pair Default Board Termination CLKout0 LVPECL CLKout1 LVPECL CLKout2 LVDS LVCMOS CLKout3 LVDS LVCMOS CLKo...

Page 15: ... Main power supply input for the evaluation board A 3 9 V DC power source applied to this SMA will by default source the onboard LDO regulators that power the inner layer planes that supply the LMK04906B and its auxiliary circuits e g VCXO The LMK04906B contains internal voltage regulators for the VCO PLL and other internal blocks The clock outputs do not have an internal regulator so a clean powe...

Page 16: ...ck input selected in CodeLoader The clock input selection mode can be programmed on the Bits Pins tab via the CLKin_Select_MODE control Refer to the LMK04906 Family Datasheet section Input Clock Switching for more information AC coupled Input Clock Swing Levels Input Mode Min Max Units Differential Bipolar or CMOS 0 5 3 1 Vpp Single Ended 0 25 2 4 Vpp External Feedback Input FBCLKin for 0 Delay CL...

Page 17: ...mmodate the desired VCXO device A single ended or differential signal may be used to drive the OSCin OSCin pins and must be AC coupled If operated in single ended mode the unused input must be connected to GND with 0 1 uF Refer to the LMK04906 Family Datasheet section Electrical Characteristics for PLL2 Reference Input OSCin specifications Test point VTUNE1_TP Analog Output Tuning voltage output f...

Page 18: ...6 Family Datasheet section Status Pins and Digital Lock Detect for more information Note Before a high frequency internal signal e g PLL divider output signal is selected by LD_MUX it is suggested to first remove the 270 ohm resistor to prevent the LED from loading the output Test point Holdover_TP CMOS Output Programmable status output pin By default set to the output holdover mode status signal ...

Page 19: ...Switching Pin Select Mode When CLKin_SELECT_MODE is 3 the Status_CLKinX pins select which clock input is active as follows Status_CLKin1 Status_CLKin0 Active Clock 0 0 CLKin0 0 1 CLKin1 1 0 CLKin2 1 1 Holdover Input Clock Switching Auto with Pin Select When CLKin_SELECT_MODE is 6 the active clock is selected using the Status_CLKinX pins upon an input clock switch event as follows Status_CLKin1 Sta...

Page 20: ...fault CodeLoader mode SYNC will asserted when the SYNC pin is low and the outputs to be synchronized will be held in a logic low state When SYNC is unasserted the clock outputs to be synchronized are activated and will be initially phase aligned with each other except for outputs programmed with different digital delay values A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in ...

Page 21: ... the E5052 is superior for phase noise measurements At frequencies less than 100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A s internal local oscillator performance not the device under test Oscilloscope To measure the output clocks for AC performance such as rise time or fall time propagation delay or skew it is suggested to use a real time os...

Page 22: ...tup tab the user may select the type of communication port LPT or USB that will be used to program the device on the evaluation board If parallel port is selected the user should ensure that the correct port address is entered The Pin Configuration field is hardware dependent and needs to be configured for use with the USB2ANY uWIRE interface Figure 8 shows the settings required for this configura...

Page 23: ... Tab The Clock Outputs tab allows the user to control the output channel blocks including Clock Group Source from either VCO or OSCin via OSC Mux1 and OSC Mux2 Channel Powerdown affects digital and analog delay clock divider and buffer blocks Digital Delay value and Half Step Clock Divide value Analog Delay value and Delay bypass enable per output Clock Output format per output ...

Page 24: ...s will bring the PLL2 tab into focus where these values may be modified if needed Clicking on the values in the box containing the Internal Loop Filter component R3 C3 R4 C4 allow one to step through the possible values Left click to increase the component value and right click to decrease the value These values can also be changed in the Bits Pins tab The Reference Oscillator value field may be c...

Page 25: ...Revised December 2013 LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs SNAU126A 25 Copyright 2013 Texas Instruments Incorporated Figure 10 Warning message indicating mismatch between ...

Page 26: ...he user to change the following parameters in Table 7 Table 7 Registers Controls and Descriptions in PLL1 tab Control Name Register Name Description Reference Oscillator Frequency MHz n a CLKin frequency of the selected reference clock Phase Detector Frequency MHz n a PLL1 Phase Detector Frequency PDF This value is calculated as PLL1 PDF CLKin Frequency PLL1_R CLKinX_PreR_DIV where CLKinX_PreR_DIV...

Page 27: ..._N PLL1 N Counter value 1 to 16383 Phase Detector Polarity PLL1_CP_POL PLL1 Phase Detector Polarity Click on the polarity sign to toggle polarity or Charge Pump Gain PLL1_CP_GAIN PLL1 Charge Pump Gain Left click right click to increase decrease charge pump gain 100 200 400 1600 uA Charge Pump State PLL1_CP_TRI PLL1 Charge Pump State Click to toggle between Active and Tri State Setting the PLL1 VCO...

Page 28: ...equency from the External VCXO or Crystal Phase Detector Frequency MHz n s PLL2 Phase Detector Frequency PDF This value is calculated as PLL2 PDF OSCin Frequency 2EN_PLL2_REF_2X PLL2_R VCO Frequency MHz n a Internal VCO Frequency should be within the allowable range of the LMK04906B device This value is calculated as VCO Frequency PLL2 PDF PLL2_N PLL2_P VCO divider value Doubler EN_PLL2_REF_2X PLL...

Page 29: ...A Charge Pump State PLL2_CP_TRI PLL2 Charge Pump State Click to toggle between Active and Tri State Changes made on this tab will be reflected in the Clock Outputs tab The VCO Frequency should conform to the specified internal VCO frequency range for the LMK04906B device per Table 2 Bits Pins Tab Figure 13 Bits Pins tab The Bits Pins tab allows the user to program bits directly many of which are n...

Page 30: ...SCin_FREQ to the proper frequency range VCO_MUX Selects between VCO and VCO divider to drive the clock distribution path The VCO divider is only valid if MODE is selecting the Internal VCO uWire_LOCK When checked no other uWire programming will have effect Must be unchecked to enable uWire programming of registers R0 to R30 CLKin CLKin_Select_MODE Selects operational mode for how the device select...

Page 31: ... PLL2 DLD is true NO_SYNC_CLKoutX_Y Synchronization will not affect selected clock outputs where X even numbered output and Y odd numbered output SYNC_QUAL Sets the SYNC to qualify mode for dynamic digital delay EN_SYNC Must be set when using SYNC but may be cleared after the SYNC event When using dynamic digital delay SYNC_QUAL 1 EN_SYNC must always be set Changing this value from 0 to 1 can caus...

Page 32: ...from GND in 50mV steps at which a clock switch event is generated If Holdover mode is enabled it will be engaged upon the clock switch event NOTE EN_VTUNE_RAIL_DET must be enabled for this to be valid DAC_HIGH_TRIP Value from VCC 3 3V in 50mV steps at which clock switch event is generated If Holdover mode is enabled it will be engaged upon the clock switch event NOTE EN_VTUNE_RAIL_DET must be enab...

Page 33: ...error as specified by PLL2_WND_SIZE for this many cycles before PLL2 digital lock detect is asserted EN_PLL2_REF_2X Enables the doubler block to doubles the reference frequency into the PLL2 R counter This can allow for frequency of 2 3 2 5 etc of OSCin to be used at the phase detector of PLL2 PLL2_N_CAL The PLL2_N_CAL register contains the N value used for the VCO calibration routine Except durin...

Page 34: ... Tab Figure 14 Registers Tab The Registers tab shows the value of each register This is convenient for programming the device to the desired settings then exporting to a text file the register values in hexadecimal for use in your own application By clicking in the bit field it is possible to manually change the value of registers by typing 1 and 0 ...

Page 35: ...itions used for output clock phase noise measurements with the Epson 25 MHz VCXO Table 10 LMK04906B Test Conditions Parameter Value PLL1 Reference clock input CLKin1 single ended input CLKin1 AC coupled to GND PLL1 Reference Clock frequency 125 MHz PLL1 Phase detector frequency 2083 33 MHz PLL1 Charge Pump Gain 400 uA VCXO frequency 25 MHz PLL2 phase detector frequency 50 MHz PLL2 Charge Pump Gain...

Page 36: ...f 20 MHz at 25 MHz rms fs Low Offset Jitter 10 Hz 515 4 100 Hz 60 5 1 kHz 36 2 10 kHz 35 0 100 kHz 34 5 1 MHz 32 9 10 MHz 22 7 Clock Output Measurement Technique The same technique was used to measure phase noise for all three output types available on the programmable OSCout and CLKout buffers This was achieved by connection the differential outputs to a Prodyn GXXX Balun and measuring the side s...

Page 37: ...CLKout frequency is 125 MHz LMK04906B CLKout Phase Noise Figure 16 LMK04906B CLKout Phase Noise Table 13 LMK04906B Phase Noise dBc Hz Phase Noise and RMS Jitter fs Offset 625 MHz LVPECL 1 6 156 25 MHz LVPECL 1 6 125 MHz LVPECL 1 6 100 Hz 76 0 88 0 90 8 1 kHz 103 2 115 6 117 1 10 kHz 118 1 130 2 132 2 100 kHz 121 5 134 0 136 0 800 kHz 140 5 152 5 154 3 1 MHz 142 7 154 4 156 1 10 MHz 154 6 161 1 161...

Page 38: ...38 SNAU126A LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs Revised December 2013 Copyright 2013 Texas Instruments Incorporated Appendix C Schematics Power Supplies ...

Page 39: ...than and equal to 200 are placed on bottom of PCB 10µF C37 0 1µF C39 CLKout0_P CLKout0_N CLKout1_P CLKout1_N CLKout2_P CLKout2_N CLKin0_P CLKin0_N CLKin1_P CLKin1_N CLKin2_P CLKin2_N Status_Hold Status_LD Status_CLKin0 Status_CLKin1 CLKout5_N CLKout5_P CLKout4_N CLKout4_P CLKout3_N CLKout3_P SYNC 0 R35 DNP uWire_DATA uWire_CLK uWire_LE OSCout0_N OSCout0_P Vcc1_VCO Vcc2_CLKout_CG1 Vcc3_CLKout_CG2 V...

Page 40: ... CLKin1 Impedance Matching and Attenuation CLKin1 0 R2 270 R4 DNP 0 1µF C2 0 1µF C10 0 1µF C6 DNP 100 R5 0 1µF C1 0 R8 0 1µF C9 CLKin0 Impedance Matching and Attenuation 270 R11 DNP 0 1µF C11 DNP 0 1µF C25 0 1µF C28 270 R29 DNP 270 R33 DNP CLKin2 Impedance Matching and Attenuation Vcc_VCO 100pF C17 DNP 0 1µF C16 0 R15 DNP CLKin0_P CLKin0_N CLKin1_P CLKin1_N CLKin2_P CLKin2_N 0 1µF C27 0 1µF C24 0 ...

Page 41: ...Revised December 2013 LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs SNAU126A 41 Copyright 2013 Texas Instruments Incorporated Clock Outputs OSCout0 CLKout0 to CLKout5 ...

Page 42: ...42 SNAU126A LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs Revised December 2013 Copyright 2013 Texas Instruments Incorporated uWire Header Logic I O Ports and Status LEDs ...

Page 43: ...AP CERM 82pF 50V 10 C0G NP0 0603 Kemet C0603C820K5GACTU 1 9 C10 C15 C16 C19 C24 C25 C27 C28 C30 C39 C40 C47 C48 C49 C50 C51 C52 C53 C54 C55 C57 C58 C59 C60 C63 C69 C78 C81 CAP CERM 0 1uF 25V 5 X7R 0603 Kemet C0603C104J3RACTU 28 10 C12 CAP CERM 0 1µF 25V 10 X7R 0603 Kemet C0603C104K3RACTU 1 11 C37 C61 C67 C73 C86 C2_VCXO C2A_VCXO CAP CERM 10uF 10V 10 X5R 0805 Kemet C0805C106K8PACTU 7 12 C56 C65 C72...

Page 44: ...m 500 mA 0603 Murata BLM18AG121SN1D 10 24 R2 R8 R13 R14 R16 R27 R31 R42 R43 R99 R101 R105 R120 R123 RES 0 ohm 5 0 1W 0603 Vishay Dale CRCW06030000Z0EA 14 25 R2_VCO RES 680 ohm 5 0 1W 0603 Vishay Dale CRCW0603680RJNEA 1 26 R2_VCXO RES 1k ohm 5 0 1W 0603 Vishay Dale CRCW06031K00JNEA 1 27 R5 R30 RES 100 ohm 5 0 1W 0603 Vishay Dale CRCW0603100RJNEA 2 28 R19 RES 18 ohm 5 0 1W 0603 Vishay Dale CRCW06031...

Page 45: ...00SD 3 3 1 43 uWire Low Profile Vertical Header 2x5 0 100 FCI 52601 G10 8LF 1 44 C2p_VCO C17 C20 C41 C42 C43 C44 C45 C46 C76 C79 CAP CERM 100pF 50V 5 C0G NP0 0603 Kemet C0603C101J5GACTU 0 45 C6 C38 CAP CERM 0 1uF 25V 5 X7R 0603 Kemet C0603C104J3RACTU 0 46 C7 C8 C11 C13 C14 C18 C21 C22 C23 C35 C66 C70 C77 C80 CAP CERM 0 1uF 16V 10 X7R 0603 Kemet TDK C0603C104K4RACTU C1608X7R1C104K 0 47 C26 CAP CERM...

Page 46: ...61 R17 R18 RES 120 ohm 5 0 1W 0603 Vishay Dale CRCW0603120RJNEA 0 62 R25 R26 R38 RES 10k ohm 5 0 1W 0603 Vishay Dale CRCW060310K0JNEA 0 63 R36 R39 RES 4 7k ohm 5 0 1W 0603 Vishay Dale CRCW06034K70JNEA 0 64 R37 R66 R67 R68 R75 R76 R77 R78 R80 R84 R87 R88 R91 R92 R95 RES 51 ohm 5 0 1W 0603 Vishay Dale CRCW060351R0JNEA 0 65 R96 R97 R98 Ferrite Murata BLM18HE102SN1D 0 66 R118 RES 51k ohm 5 0 1W 0603 V...

Page 47: ...4003 Dielectric 16 mils RF Ground plane 1 oz FR4 4 mils Power plane 1 1 oz FR4 12 6 mils Ground plane 1 oz FR4 8 mils Power Plane 2 1 oz FR4 12 mils Bottom Layer copper clad for thermal relief 2 oz RO4003 Er 3 3 16 mil Top Layer LMK049xxENG GTL RF Ground plane LMK049xxENG G1 FR4 Er 4 8 4 mil Power plane 1 LMK049xxENG G2 FR4 12 6 mil Ground plane LMK049xxENG GP1 FR4 12 mil Bottom Layer LMK049xxENG ...

Page 48: ...48 SNAU126A LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs Revised December 2013 Copyright 2013 Texas Instruments Incorporated Appendix F PCB Layout Layer 1 Top ...

Page 49: ...Revised December 2013 LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs SNAU126A 49 Copyright 2013 Texas Instruments Incorporated Layer 2 RF Ground Plane Inverted ...

Page 50: ...50 SNAU126A LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs Revised December 2013 Copyright 2013 Texas Instruments Incorporated Layer 3 Vcc Planes ...

Page 51: ...Revised December 2013 LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs SNAU126A 51 Copyright 2013 Texas Instruments Incorporated Layer 4 Ground Plane Inverted ...

Page 52: ...52 SNAU126A LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs Revised December 2013 Copyright 2013 Texas Instruments Incorporated Layer 5 Vcc Planes 2 ...

Page 53: ...Revised December 2013 LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs SNAU126A 53 Copyright 2013 Texas Instruments Incorporated Layer 6 Bottom ...

Page 54: ...54 SNAU126A LMK04906 Family Low Noise Clock Jitter with Dual Loop PLLs Revised December 2013 Copyright 2013 Texas Instruments Incorporated Layers 1 and 6 Top and Bottom Composite ...

Page 55: ...LPT port must not be in an improper mode The PC must be rebooted after install for LPT support to work properly Correct LPT Port Address To determine the correct LPT port in Windows open the device manager On Windows XP Start Settings Control Panel System Hardware tab Device Manager and check the LPT port under the Ports COM LPT node of the tree It can be helpful to confirm that the LPT port is ma...

Page 56: ...improperly It is recommended to use the simple Output only mode of the LPT port This can be set in the BIOS of the computer Common terms for this desired parallel port mode are Normal Output or AT It is possible to enter BIOS setup during the initial boot up sequence of the computer Legacy Board Port Setup If LPT communication with the LMK04906B EVM is required then the following configuration sho...

Page 57: ...e detector frequency of PLL1 i If not examine PLL1 register N programming ii If not examine physical OSCin input Naturally the output frequency of the above two items PLL 1 R Divider 2 and PLL 1 N Divider 2 on LD pin should be the same frequency 5 Program LD_MUX PLL1_DLD 6 Confirm the LD pin output is high i If high then PLL1 is locked continue to PLL2 operation locking 7 If LD pin output is low b...

Page 58: ...i If not examine PLL2_R programming ii If not examine physical OSCin input 3 Program LD_MUX PLL2_N 2 4 Confirm that LD pin output is half the expected phase detector frequency of PLL2 i If not confirm OSCin_FREQ is programmed to OSCin frequency ii If not examine PLL2_N programming Naturally the output frequency of the above two items should be the same frequency 5 Program LD_MUX PLL2 DLD 6 Confirm...

Page 59: ...odeloader is the software used to communicate with the EVM Please download the latest version from TI com http www ti com tool codeloader This EVM can be controlled through the uWire interface on board There are two options in communicating with the uWire interface from the computer OPTION 1 Open Codeloader exe Click Select Device Click Port Setup tab Click LPT in Communication Mode OPTION 2 ...

Page 60: ...pin 7 LMK030xx A0 C1 E5 F1 G1 H1 SYNC pin 7 LMK02000 A0 C1 E5 F1 G1 H1 SYNC pin 7 LMK0480x A0 B2 C3 E5 F0 G0 H1 Status_CLKin1 pin 3 LMK04816 4906 A0 B2 C3 E5 F0 G0 H1 Status_CLKin1 pin 3 LMK01801 A0 B4 C5 E2 F0 G0 H1 Test pin 3 SYNC0 pin 10 LMK0482x prelease A0 B5 C3 D2 E4 F0 G0 H1 CLKin1_SEL pin 6 Reset pin 10 LMX2531 A0 E5 F2 G1 H2 Trigger pin 1 LMX2485 7 A0 C1 E5 F2 G1 H0 ENOSC pin 7 CE pin 10 ...

Page 61: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

Page 62: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments LMK04906BEVAL NOPB ...

Reviews:

No comments

Brands by name

Popular brands

Load more brands