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Texas Instruments LMK04826 Manual Download Page 47

R

CLKinX

CLKinX*

 

Phase 

Detector

PLL1

External VCXO 

or Tunable 

Crystal

R

N

Phase 

Detector

PLL2

Dual

Internal

VCOs

External

Loop Filter

Input 

Buffer

 

C

Po

u

t1

OSCout
OSCout*

LMK0482x

CPout2

Divider

Digital Delay

Analog Delay

SDCLKoutY

SDCLKoutY*

 

DCLKoutX

DCLKoutX*

 

Partially 

Integrated 

Loop Filter

7 Device

Clocks

External 

Loop Filter

PLL1

PLL2

7 blocks

Up to 3 

inputs

N

O

SC

in

Internal or external loopback, user programmable

SYSREF

Analog Delay

Digital Delay

1 Global SYSREF Divider

7 SYSREF 

or Device 

Clocks

Up to 1 OSCout

LMK04821, LMK04826, LMK04828

www.ti.com

SNAS605AR – MARCH 2013 – REVISED DECEMBER 2015

9.4.2 0-DELAY Dual PLL

Figure 18

illustrates the use case of cascaded 0-delay dual loop mode. This configuration differs from dual loop

mode

Figure 17

in that the feedback for PLL2 is driven by a clock output instead of the VCO output.

Figure 19

illustrates the use case of nested 0-delay dual loop mode. This configuration is similar to the dual PLL in

DUAL

PLL

except that the feedback to the first PLL is driven by a clock output. This causes the clock outputs to have

deterministic phase relationship with the clock input. Since all the clock outputs can be synchronized together, all
the clock outputs can share the same deterministic phase relationship with the clock input signal. The feedback
to PLL1 can be connected internally as shown using CLKout6, CLKout8, SYSREF, or externally using FBCLKin
(CLKin1).

It is also possible to use an external VCO in place of PLL2's internal VCO; but one less CLKin is available as a
reference and external 0-delay feedback is not available.

LMK04821 includes VCO1 divider on VCO1 output.

Figure 18. Simplified Functional Block Diagram for Cascaded 0-delay Dual Loop Mode

Table 6. Cascaded 0-delay Dual Loop Mode Register Configuration

REGISTER

FIELD

FUNCTION

VALUE

SELECTED VALUE

ADDRESS

PLL1_NCLK_MUX

0x13F

Selects the input to the PLL1 N divider.

0

OSCin

PLL2_NCLK_MUX

0x13F

Selects the input to the PLL2 N divider

1

Feedback Mux

FB_MUX_EN

0x13F

Enables the Feedback Mux.

1

Feedback Mux Enabled

Select between DCLKout6,

FB_MUX

0x13F

Selects the output of the Feedback Mux.

0, 1, or 2

DCLKout8, SYSREF

OSCin_PD

0x140

Powers down the OSCin port.

0

Powered up

CLKin0_OUT_MUX

0x147

Selects where the output of CLKin0 is directed.

0

PLL1

CLKin1_OUT_MUX

0x147

Selects where the output of CLKin1 is directed.

0 or 2

Fin or PLL1

VCO_MUX

0x138

Selects the VCO 0, 1 or an external VCO

0 or 1

VCO 0 or VCO 1

Copyright © 2013–2015, Texas Instruments Incorporated

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Product Folder Links:

LMK04821 LMK04826 LMK04828

Summary of Contents for LMK04826

Page 1: ...Latinum PLL Architecture limited to JESD204B applications each of the 14 PLL1 outputs can be individually configured as high Up to 3 Redundant Input Clocks performance outputs for traditional clocking systems Automatic and Manual Switch Over Modes The high performance combined with features like the ability to trade off between power or performance Hitless Switching and LOS dual VCOs dynamic digit...

Page 2: ...onal Block Diagram 32 Information 105 4 Revision History Changes from Revision AQ August 2014 to Revision AR Page Added Support for 105 C thermal pad temperature 1 Changed from I O to I for pin 6 in Pin Functions table 7 Deleted programmable status pin in Description column for pin 6 in Pin Functions table 7 Changed from No connection to Do not connect for pins 7 8 9 in Pin Functions table 7 Chang...

Page 3: ... for VCO0 16 Added 245 76 MHz as frequency for LMK04828B phase noise data L f CLKout for VCO1 16 Added values for LMK04821 under CLKout Closed Loop Jitter Specifications a Commercial Quality VCXO 17 Added SDCLKoutY_HS 0 for tsJESD204B in Electrical Characteristics 19 Added Propagation Delay from CLKin0 to SDCLKoutY in Electrical Characteristics 19 Added footnote that LMK04821 has no DCLKoutX or SD...

Page 4: ...rom Core line 102 Added VCO1 Icc including VCO1 Divider for LMK04821 102 Changed VCO1 Icc and power dissipated for LMK04828B 26B from 6 mA to 13 5 mA and 19 8 mW to 44 55 mW 102 Changes from Revision AO March 2013 to Revision AP Page Changed datasheet title from LMK04828 to LMK0482xB 1 Changed LMK04828 family to LMK04820 family 1 Changed image from LMK04828B to LMK0482xB 1 Added LMK04826 to Device...

Page 5: ...B 46 Changed corrected value of PLL2_P selection to be 0 to correspond with register programming definition 46 Changed image from LMK04828 to LMK0482xB 47 Changed image from LMK04828 to LMK0482xB 48 Added LMK04826 register setting 55 Added LMK04826 register setting 91 Added LMK04826 register setting 92 Copyright 2013 2015 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folde...

Page 6: ...to 1540 MHz VCO1_DIV 3 974 to 1026 MHz VCO1_DIV 4 730 to 770 MHz VCO1_DIV 5 LMK04821 Up to 3 Up to 1 14 1930 to 2075 MHz 584 to 616 MHz VCO1_DIV 6 487 to 513 MHz VCO1_DIV 7 418 to 440 MHz VCO1_DIV 8 365 to 385 MHz LMK04826B Up to 3 Up to 1 14 1840 to 1970 MHz 2440 to 2505 MHz LMK04828B Up to 3 Up to 1 14 2370 to 2630 MHz 2920 to 3080 MHz 1 OSCout may also be third clock input CLKin2 6 Submit Docum...

Page 7: ...www ti com SNAS605AR MARCH 2013 REVISED DECEMBER 2015 6 Pin Configuration and Functions NKD Package 64 Pin WQFN Top View Pin Functions PIN I O TYPE DESCRIPTION 1 NO NAME DCLKout0 1 2 O Programmable Device clock output 0 DCLKout0 SDCLKout1 3 4 O Programmable SYSREF Device clock output 1 SDCLKout1 5 RESET GPO I CMOS Device reset input or GPO 6 SYNC SYSREF_REQ I CMOS Synchronization input or SYSREF_R...

Page 8: ...wer supply for OSCout port OSCout OSCout Buffered output of OSCin port 40 41 I O Programmable CLKin2 CLKin2 Reference Clock Input Port 2 for PLL1 42 Vcc8_OSCin PWR Power supply for OSCin 43 44 OSCin OSCin I ANLG Feedback to PLL1 Reference input to PLL2 AC coupled 45 Vcc9_CP2 PWR Power supply for PLL2 Charge Pump 46 CPout2 O ANLG Charge pump 2 output 47 Vcc10_PLL2 PWR Power supply for PLL2 48 Statu...

Page 9: ...250 V CDM allows safe manufacturing with a standard ESD control process Manufacturing with less than 250 V CDM is possible with the necessary precautions Pins listed as 250 V may actually have higher performance 7 3 Recommended Operating Conditions over operating free air temperature range unless otherwise noted MIN TYP MAX UNIT TJ Junction Temperature 125 C TA Ambient Temperature 40 25 85 C TPCB ...

Page 10: ...Kin Single ended Input Voltage AC coupled to CLKinX CLKinX AC coupled to Ground 0 35 2 4 Vpp CLKinX_TYPE 1 MOS Each pin AC coupled CLKin0 1 2 0 mV CLKinX_TYPE 0 Bipolar DC offset voltage between CLKinX CLKinX CLKinX CLKinX Each pin AC coupled CLKin0 1 VCLKinX offset 55 mV CLKinX_TYPE 1 MOS DC offset voltage between Each pin AC coupled 20 mV CLKin2 CLKin2 CLKin2 CLKin2 CLKinX_TYPE 1 MOS VCLKin VIH ...

Page 11: ...harge Pump Voltage TA 25 C Charge Pump Current vs ICPout1 TEMP 4 Temperature Variation Charge Pump TRI STATE Leakage ICPout1 TRI 0 5 V VCPout VCC 0 5 V 5 nA Current PLL 1 f Noise at 10 kHz offset PLL1_CP_GAIN 350 µA 117 PN10kHz Normalized to 1 GHz Output dBc Hz PLL1_CP_GAIN 1550 µA 118 Frequency PLL1_CP_GAIN 350 µA 221 5 PN1Hz Normalized Phase Noise Contribution dBc Hz PLL1_CP_GAIN 1550 µA 223 PLL...

Page 12: ...0 µA 118 PN10kHz Normalized to dBc Hz PLL2_CP_GAIN 3200 µA 121 1 GHz Output Frequency PLL2_CP_GAIN 400 µA 222 5 Normalized Phase Noise Contribution PN1Hz dBc Hz 10 PLL2_CP_GAIN 3200 µA 227 9 A specification in modeling PLL in band phase noise is the 1 f flicker noise LPLL_flicker f which is dominant close to the carrier Flicker noise has a 10 dB decade slope PN10kHz is normalized to a 10 kHz offse...

Page 13: ... permitted to 125 C 12 assure continuous lock 11 The VCO1 divider VCO1_DIV in register 0x174 can be programmed to 2 to 8 resulting in a lower effective VCO frequency range as shown in Device Configuration Information 12 Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last ...

Page 14: ...4 LVPECL16 w 240 Ω 161 8 LVPECL20 w 240 Ω 162 0 LCPECL 161 7 LVDS 157 5 HSDS 6 mA 158 9 HSDS 8 mA 159 8 LMK04826 VCO1 Noise Floor L f CLKout 245 76 MHz HSDS 10 mA 160 3 dBc Hz 20 MHz Offset 14 LVPECL16 w 240 Ω 160 8 LVPECL20 w 240 Ω 160 7 LCPECL 160 7 13 Data collected using a Prodyn BIB 100G balun Loop filter is C1 47 pF C2 3 9 nF R2 620 Ω C3 10 pF R3 200 Ω C4 10 pF R4 200 Ω PLL1_CP 450 µA PLL2_C...

Page 15: ...PECIFICATIONS a COMMERCIAL QUALITY VCXO 16 Offset 1 kHz 126 9 Offset 10 kHz 133 5 LMK04821 Offset 100 kHz 135 4 VCO0 L f CLKout Offset 1 MHz 149 8 dBc Hz SSB Phase Noise 13 LVDS 158 1 245 76 MHz Offset 10 MHz HSDS 8 mA 161 1 LVPECL16 w 240 Ω 161 7 Offset 1 kHz 126 8 Offset 10 kHz 133 4 LMK04821 Offset 100 kHz 135 4 VCO1 L f CLKout Offset 1 MHz 151 8 dBc Hz SSB Phase Noise 13 LVDS 157 2 245 76 MHz ...

Page 16: ...LVPECL16 w 240 Ω 161 5 Offset 10 kHz 134 3 Offset 100 kHz 133 7 LVDS 152 5 LMK04826B Offset 1 MHz VCO1 HSDS 8 mA L f CLKout 153 6 dBc Hz SSB Phase Noise 14 LVPECL16 w 240 Ω 245 76 MHz LVDS 157 3 Offset 10 MHz HSDS 8 mA 159 6 LVPECL16 w 240 Ω 160 5 Offset 1 kHz 124 3 Offset 10 kHz 134 7 LMK04828 Offset 100 kHz 136 5 VCO0 L f CLKout Offset 1 MHz 148 4 dBc Hz SSB Phase Noise 15 LVDS 156 4 245 76 MHz ...

Page 17: ...rated RMS Jitter 13 91 BW 12 kHz to 20 MHz LCPECL w 240 Ω 91 BW 12 kHz to 20 MHz CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO continued 16 LVDS BW 100 Hz to 20 MHz 106 LVDS BW 12 kHz to 20 MHz 104 HSDS 8 mA BW 100 Hz to 20 MHz 99 HSDS 8 mA BW 12 kHz to 20 MHz 97 LVPECL16 w 240 Ω LMK04826B VCO0 99 BW 100 Hz to 20 MHz fCLKout 245 76 MHz fs rms Integrated RMS Jitter 14 LVPECL16 ...

Page 18: ...9 LVPECL16 w 240 Ω LMK04828 VCO0 98 BW 100 Hz to 20 MHz fCLKout 245 76 MHz fs rms Integrated RMS Jitter 15 LVPECL20 w 240 Ω 95 BW 12 kHz to 20 MHz LCPECL w 240 Ω 96 BW 100 Hz to 20 MHz LCPECL w 240 Ω 93 BW 12 kHz to 20 MHz JCLKout LVDS BW 100 Hz to 20 MHz 108 LVDS BW 12 kHz to 20 MHz 105 HSDS 8 mA BW 100 Hz to 20 MHz 98 HSDS 8 mA BW 12 kHz to 20 MHz 94 LVPECL16 w 240 Ω LMK04828 VCO1 93 BW 100 Hz t...

Page 19: ..._PD 0 tPDCLKin0_ Propagation Delay from CLKin0 to SDCLKout1_DDLY 0 Bypass 0 65 ns SDCLKout1 SDCLKout1 SDCLKout1_MUX 1 SR EN_SYNC 1 LVPECL16 w 240 Ω fADLYmax Maximum analog delay frequency DCLKoutX_MUX 4 1536 MHz LVDS CLOCK OUTPUTS DCLKoutX SDCLKoutY and OSCout VOD Differential Output Voltage 395 mV Change in Magnitude of VOD for ΔVOD 60 60 mV T 25 C DC measurement complementary output states AC co...

Page 20: ...TPUTS DCLKoutX and SDCLKoutY VCC VOH 0 99 T 25 C DC measurement Termination 50 Ω to VCC VOL VCC 1 43 V 1 97 VOD 980 mVpp Change in VOD for complementary ΔVOD 115 115 mVpp output states LVPECL CLOCK OUTPUTS DCLKoutX and SDCLKoutY 20 to 80 Output Rise RL 100 Ω emitter resistors 240 Ω to GND TR TF 150 ps DCLKoutX_TYPE 4 or 5 80 to 20 Output Fall Time 1600 or 2000 mVpp 1600 mVpp LVPECL CLOCK OUTPUTS D...

Page 21: ...ET_TYPE 3 4 or 6 DIGITAL OUTPUT SDIO IOH 500 µA During SPI read VCC VOH High Level Output Voltage V SDIO_RDBK_TYPE 0 0 4 IOL 500 µA During SPI read VOL Low Level Output Voltage 0 4 V SDIO_RDBK_TYPE 0 or 1 DIGITAL INPUTS CLKinX_SEL RESET GPO SYNC SCK SDIO or CS VIH High Level Input Voltage 1 2 VCC V VIL Low Level Input Voltage 0 4 V DIGITAL INPUTS CLKinX_SEL CLKin_SELX_TYPE 0 5 5 High Impedance Hig...

Page 22: ... 25 C at the Recommended Operating Conditions and are not assured PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High Level Input Current VIH VCC 5 5 µA IIL Low Level Input Current VIL 0 5 5 µA DIGITAL INPUT TIMING tHIGH RESET pin held high for device reset 25 ns 22 Submit Documentation Feedback Copyright 2013 2015 Texas Instruments Incorporated Product Folder Links LMK04821 LMK04826 LMK04828 ...

Page 23: ...g edge to valid read back data See Figure 1 20 ns 1 20 MHz Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK signal On the rising edge of the CS signal the register is sent from the shift register to the register addressed A slew rate of at least 30 V µs is recommended for these signals After programming is complete the CS signal shoul...

Page 24: ...100G For Figure 6 and Figure 7 Balun ADT2 1T VCO_MUX 0 VCO0 PLL2 Loop Filter Bandwidth 288 kHz VCO_MUX 1 VCO1 VCO1_DIV 0 2 VCO0 1966 08 MHz PLL2 Phase Margin 72 VCO 2949 12 MHz PLL2 Loop Filter Bandwidth 221 kHz DCLKout2_DIV 8 DCLKout2_DIV 6 PLL2 Phase Margin 70 Figure 2 LMK04821 DCLKout2 Phase Noise Figure 3 LMK04821 DCLKout2 Phase Noise VCO_MUX 0 VCO0 PLL2 Loop Filter Bandwidth 303 kHz VCO_MUX 1...

Page 25: ...out2_3_ODL 0 LVPECL20 with 240 Ω emitter resistors DCLKout2 Frequency 245 76 MHz DCLKout2_MUX 0 Divider For Figure 2 through Figure 5 Balun Prodyn BIB 100G For Figure 6 and Figure 7 Balun ADT2 1T VCO_MUX 0 VCO0 PLL2 Loop Filter Bandwidth 344 kHz VCO_MUX 1 VCO1 PLL2 Loop Filter Bandwidth 233 kHz VCO0 2457 6 MHz PLL2 Phase Margin 73 VCO 2949 12 MHz PLL2 Phase Margin 70 DCLKout2_DIV 10 DCLKout2_DIV 1...

Page 26: ...harge Pump Source Current at VCPout VCC 2 I6 Charge Pump Source Current at VCPout ΔV ΔV Voltage offset from the positive and negative supply rails Defined to be 0 5 V for this device 8 1 1 Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage 8 1 2 Charge Pump Sink Current Vs Charge Pump Output Source Current Mismatch 8 1 3 Charge Pump Output Current Magnitude Variation Vs A...

Page 27: ...t is VSS and is a calculated parameter Nowhere in the IC does this signal exist with respect to ground it only exists in reference to its differential pair VSS can be measured directly by oscilloscopes with floating references otherwise this value can be calculated as twice the value of VOD as described in the first description Figure 8 illustrates the two different definitions side by side for in...

Page 28: ...good low offset frequency phase noise of the reference VCXO or tunable crystal Ultra low jitter is achieved by allowing the external VCXO or Crystal s phase noise to dominate the final output phase noise at low offset frequencies and the internal VCO s phase noise to dominate the final output phase noise at high offset frequencies This results in best overall phase noise and jitter performance 9 1...

Page 29: ...CO1 frequency of 2949 12 MHz and a divide of 8 frequencies as low as 11 52 MHz can be achieved Using the VCO1_DIV will limit maximum output frequency from any output to VCO1 frequency divided by VCO1_DIV value When using VCO1 the output frequency from the VCO1_DIV will define digital delay resolution The VCO1_DIV divider also impacts the total N divide value for PLL2 when VCO1 is selected this sho...

Page 30: ...additional local digital delay for unique phase adjustment of each SYSREF clock The local analog delay allows for 150 ps steps The local digital delay and SYSREF_HS bit allows the each individual SYSREF output to be delayed from 1 5 to 11 VCO cycles The delay step can be as small as half the period of the clock distribution path by using the DCLKoutX_HS bit For example 2 GHz VCO frequency results ...

Page 31: ... to the phase of a clock selected by the feedback mux The 0 delay feedback may performed with an internal feedback from CLKout6 CLKout8 SYSREF or with an external feedback loop into the FBCLKin port as selected by the FB_MUX Without using 0 delay mode there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value Using an external 0 d...

Page 32: ... Reference Control Divider 8 to 8191 Status_LD1 RESET GPO CLKin_SEL0 CLKin_SEL1 Fin SCLK SDIO CS SPI Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A ...

Page 33: ... DCLKout12 SDCLKout13 SDCLKout13 SYNC System Reference Control Divider 8 to 8191 Status_LD1 RESET GPO CLKin_SEL0 CLKin_SEL1 Fin SCLK SDIO CS SPI Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A Delay Dig Delay Div 1 32 Dig Delay A Delay A D...

Page 34: ...Y_PD DCLKoutX_ADLYg_PD DCLKoutX_HSg_PD SDCLKoutY_PD CLKoutX_Y_PD SDCLKoutY _POL DCLKoutX _POL DCLKout6 8 to FB_MUX SYSREF_GBL_PD DCLKoutX_DDLY_PD CLKoutX_Y_ODL CLKoutX_Y_IDL SPI Register Legend SYSREF SYNC Clock VCO Distribution Clock LMK04821 LMK04826 LMK04828 SNAS605AR MARCH 2013 REVISED DECEMBER 2015 www ti com Functional Block Diagram continued Figure 12 Device and SYSREF Clock Output Block 34...

Page 35: ...D PLL1_DLD SYNC_PLL2_DLD PLL2_DLD PULSER MODE CLKin0 CLKin0 _OUT _MUX SYSREF_CLR OSCout FB_MUX OSCout _MUX PLL1 SYSREF_REQ_EN Note The SYNC CLKin0 input is reclocked to the Dist Path OSCin DCLKout6 DCLKout8 CLKin1 PLL1 FB_MUX SYSREF_PLSR_PD SYSREF_DDLY_PD SYSREF_PD Dist Path SPI Register Legend SYSREF SYNC Clock VCO Distribution Clock SYSREF _CLKin0 _MUX LMK04821 LMK04826 LMK04828 www ti com SNAS6...

Page 36: ...may be set as desired Table 1 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE Table 1 Some Possible SYNC Configurations NAME SYNC_MODE SYSREF_MUX OTHER DESCRIPTION SYNC Disabled 0 0 CLKin0_OUT_MUX 0 No SYNC will occur Basic SYNC functionality SYNC pin polarity is selected by SYNC_POL Pin or SPI SYNC 1 0 CLKin0_OUT_MUX 0 To achieve SYNC through SPI toggle the SYNC_POL bit Dif...

Page 37: ...or a system which is to operate with a 3000 MHz VCO frequency Use DCLKout0 and DCLKout2 to drive converters at 1500 MHz Use DCLKout4 to drive an FPGA at 150 MHz Synchronize the converters and FPGA using a two SYSREF pulses at 10 MHz 1 Program registers 0x000 to 0x1fff as desired Key to prepare for SYSREF operations a Prepare for manual SYNC SYNC_POL 0 SYNC_MODE 1 SYSREF_MUX 0 b Setup output divide...

Page 38: ...of the JEDEC JESD204B specification When in SYSREF Pulser mode programming the field SYSREF_PULSE_CNT in register 0x13E will result in the pulser sending the programmed number of pulses 9 3 2 2 2 Continuous SYSREF This mode allows for continuous output of the SYSREF clock Continuous operation of SYSREF is not recommended due to crosstalk from the SYSREF clock to device clock JESD204B is designed t...

Page 39: ...n adjusting digital delay should use dynamic digital delay 9 3 3 1 1 Fixed Digital Delay Example Assuming the device already has the following initial configurations and the application should delay DCLKout2 by one VCO cycle compared to DCLKout0 VCO frequency 2949 12 MHz DCLKout0 368 64 MHz DCLKout0_DIV 8 DCLKout2 368 64 MHz DCLKout2_DIV 8 The following steps should be followed 1 Set DCLKout0_DDLY...

Page 40: ...will advanced with respect to the other clocks Table 3 shows the recommended DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL alternate divide setting for delay by one VCO cycle The clock will output high during the DCLKoutX_DDLY_CNTH time to permit a continuous output clock The clock output will be low during the DCLKoutX_DDLY_CNTL time Table 3 Recommended DCLKoutX_DDLY_CNTH _CNTL Values for Delay by On...

Page 41: ...DCLKout2 4 Set DDLYd2_EN 1 Enable dynamic digital delay for DCLKout2 5 Set SYNC_DIS0 1 and SYNC_DIS2 0 Sync should be disabled to DCLKout0 but not DCLKout2 6 Set SYNC_MODE 3 Enable SYNC event from SPI write to DDLYd_STEP_CNT s register 7 Set SYNC_MODE 2 SYSREF_MUX 2 Setup proper SYNC settings 8 Set DDLYd_STEP_CNT 1 This begins the first adjustment Before step 8 DCLKout2 clock edge is aligned with ...

Page 42: ...put clock Manual mode will also override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is disabled with EN_CLKinX 0 If holdover is entered in this mode then the device will re lock to the selected CLKin upon holdover exit 9 3 5 2 Input Clock Switching Pin Select Mode When CLKin_SEL_MODE is 3 the pins CLKin_SEL0 and CLKin_SEL1 select which clock input is active Configur...

Page 43: ...ze ε a lock detect count increments When the lock detect count reaches a user specified value PLL1_DLD_CNT or PLL2_DLD_CNT lock detect is asserted true Once digital lock detect is true a single phase comparison outside the specified window will cause digital lock detect to be asserted false This is illustrated in Figure 16 Figure 16 Digital Lock Detect Flowchart This incremental lock detect count ...

Page 44: ...tatus_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX respectively Updates to the DAC value for the Tracked CPout1 sub mode occurs at the rate of the PLL1 phase detector frequency divided by DAC_CLK_MULT DAC_CLK_CNTR The DAC update rate should be programmed for 100 kHz to ensure DAC holdover accuracy The ability to program slow DAC update rates for example one DAC update per 4 08 ...

Page 45: ...of the system when in holdover mode in ppm is 1 Example consider a system with a 19 2 MHz clock input a 153 6 MHz VCXO with a Kv of 17 kHz V The accuracy of the system in holdover in ppm is 0 71 ppm 6 4 mV 17 kHz V 1e6 153 6 MHz 2 It is important to account for this frequency error when determining the allowable frequency error window to cause holdover mode to exit 9 3 7 5 Holdover Mode Automatic ...

Page 46: ... narrow loop bandwidth The VCXO or tunable crystal output may be buffered through the OSCout port The VCXO or tunable crystal is used as the reference to PLL2 and may be doubled using the frequency doubler The internal VCO drives up to seven divide delay blocks which drive up to 14 clock outputs Hitless switching and holdover functionality are optionally available when the input reference clock is...

Page 47: ...her all the clock outputs can share the same deterministic phase relationship with the clock input signal The feedback to PLL1 can be connected internally as shown using CLKout6 CLKout8 SYSREF or externally using FBCLKin CLKin1 It is also possible to use an external VCO in place of PLL2 s internal VCO but one less CLKin is available as a reference and external 0 delay feedback is not available LMK...

Page 48: ... clock out feedback is to PLL1 The CLKin and CLKout have the same deterministic phase relationship but the VCXO s phase will not be deterministic to the CLKin or CLKouts Table 7 Nested 0 delay Dual Loop Mode Register Configuration REGISTER FIELD FUNCTION VALUE SELECTED VALUE ADDRESS PLL1_NCLK_MUX 0x13F Selects the input to the PLL1 N divider 1 Feedback Mux PLL2_NCLK_MUX 0x13F Selects the input to ...

Page 49: ...ing the first and 0x1FFF being the last register programmed The recommended programming sequence from POR involves 1 Program register 0x000 with RESET 1 2 Program registers in numeric order from 0x000 to 0x165 Ensure the following register is programmed as follows 0x145 127 0x7F 3 Program register 0x171 to 0xAA and 0x172 to 0x02 4 If using LMK04821 program register 0x174 5 Program registers 0x17C ...

Page 50: ...0 0x107 CLKout1_FMT CLKout0_FMT _POL _POL CLKout2_3 CLKout2_3 0x108 0 DCLKout2_DIV _ODL _IDL 0x109 DCLKout2_DDLY_CNTH DCLKout2_DDLY_CNTL DCLKout2_ 0x10B DCLKout2_ADLY DCLKout2_MUX ADLY_MUX DCLKout2 SDCLKout3 SDCLKout3 0x10C 0 SDCLKout3_DDLY _HS _MUX _HS SDCLKout3 0x10D 0 0 0 SDCLKout3_ADLY _ ADLY_EN DCLKout2 DCLKout2 DCLKout2 DCLKout2 CLKout2_3 SDCLKout3 0x10E SDCLKout3_DIS_MODE _ DDLY_PD _ HSg_PD...

Page 51: ...Kout10 0x128 0 DCLKout10_DIV _11 _ODL _11_IDL 0x129 DCLKout10_DDLY_CNTH DCLKout10_DDLY_CNTL DCLKout10 0x12B DCLKout10_ADLY DCLKout10_MUX _ ADLY_MUX DCLKout10 SDCLKout11 SDCLKout11 0x12C 0 SDCLKout11_DDLY _HS _MUX _HS SDCKLout11 0x12D 0 0 0 SDCLKout11_ADLY _ ADLY_EN DCLKout10 DCLKout10 DLCLKout10 DCLKout10 CLKout10 SDCLKout11 0x12E SDCLKout11_DIS_MODE _ DDLY_PD _ HSg_PD _ ADLYg_PD _ ADLY_PD _11_PD ...

Page 52: ...LKin_SEL0_TYPE SDIO_RDBK 0x149 0 CLKin_SEL1_MUX CLKin_SEL1_TYPE _TYPE 0x14A 0 0 RESET_MUX RESET_TYPE HOLDOVER MAN_DAC 0x14B LOS_TIMEOUT LOS_EN TRACK_EN MAN_DAC 9 8 _ FORCE _EN 0x14C MAN_DAC 7 0 0x14D 0 0 DAC_TRIP_LOW 0x14E DAC_CLK_MULT DAC_TRIP_HIGH 0x14F DAC_CLK_CNTR HOLDOVER CLKin HOLDOVER HOLDOVER HOLDOVER HOLDOVER 0x150 0 0 _HITLESS _OVERRIDE _ PLL1_DET _LOS _DET _VTUNE_DET _EN _SWITCH 0x151 0...

Page 53: ...C3 0x16E PLL2_LD_MUX PLL2_LD_TYPE 0x171 1 0 1 0 1 0 1 0 0x172 0 0 0 0 0 0 1 0 0x173 0 PLL2_PRE_PD PLL2_PD 0 0 0 0 0 0x174 0 0 0 VCO1_DIV 0x17C OPT_REG_1 0x17D OPT_REG_2 RB_PLL1_ CLR_PLL1_ 0x182 0 0 0 0 0 RB_PLL1_LD LD_LOST LD_LOST RB_PLL2_ CLR_PLL2_ 0x183 0 0 0 0 0 RB_PLL2_LD LD_LOST LD_LOST RB_CLKin2_ RB_CLKin1_ RB_CLKin0_ RB_CLKin1_ RB_CLKin0_ 0x184 RB_DAC_VALUE 9 8 X SEL SEL SEL LOS LOS 0x185 R...

Page 54: ...000 BIT NAME POR DESCRIPTION DEFAULT 0 Normal Operation 7 RESET 0 1 Reset automatically cleared 6 5 NA 0 Reserved Disable 3 wire SPI mode 4 Wire SPI mode is enabled by selecting SPI Read back in one of the output MUX settings For example CLKin0_SEL_MUX 4 SPI_3WIRE_DIS 0 0 3 Wire Mode enabled 1 3 Wire Mode disabled 3 0 NA NA Reserved 9 7 1 2 POWERDOWN This register contains the POWERDOWN function T...

Page 55: ...a read only register Table 13 Register 0x006 POR BIT NAME DESCRIPTION DEFAULT 36 IC version identifier for LMK04821 7 0 ID_MASKREV 37 IC version identifier for LMK04826 32 IC version identifier for LMK04828 9 7 1 6 ID_VNDR 15 8 ID_VNDR These registers contain the vendor identifier This is a read only register Table 14 ID_VNDR Register Configuration ID_VNDR 15 0 MSB LSB 0x00C 7 0 0x00D 7 0 Table 15...

Page 56: ... 8 0 0x00 32 4 0 DCLKoutX_DIV X 6 8 1 0x01 1 1 X 8 8 X 10 8 2 0x02 2 X 12 2 30 0x1E 30 31 0x1F 31 1 Not valid if DCLKoutX_MUX 0 Divider only Not valid if DCLKoutX_MUX 3 Analog Delay Divider and DCLKoutX_ADLY_MUX 0 without duty cycle correction halfstep 9 7 2 2 DCLKoutX_DDLY_CNTH DCLKoutX_DDLY_CNTL This register controls the digital delay high and low count values for the device clock outputs Table...

Page 57: ...t 0 0x0 Divider only 1 1 0 DCLKoutX_MUX 0 Divider with Duty Cycle Correction 1 0x1 and Half Step 2 0x2 Bypass 3 0x3 Analog Delay Divider 1 DCLKoutX_DIV 1 is not valid 9 7 2 4 DCLKoutX_HS SDCLKoutY_MUX SDCLKoutY_DDLY SDCLKoutY_HS These registers set the half step for the device clock the SYSREF output MUX the SYSREF clock digital delay and half step Table 19 Registers 0x104 0x10C 0x114 0x11C 0x124 ...

Page 58: ...SYSREF output SDCLKoutY 4 0 0 Disabled _ADLY_EN 1 Enabled Sets the analog delay value for the SYSREF output Selecting analog delay adds an additional 700 ps in propagation delay Effective range is 700 ps to 2950 ps Field Value Delay Value 0 0x0 0 ps 1 0x1 600 ps SDCLKoutY 3 0 0 _ADLY 2 0x2 750 ps 150 ps from 0x1 3 0x3 900 ps 150 ps from 0x2 14 0xE 2100 ps 150 ps from 0xD 15 0xF 2250 ps 150 ps from...

Page 59: ...de is glitchless between values 1 to 23 _ADLYg_PD 1 Powerdown Powerdown the device clock analog delay feature DCLKoutX 4 1 0 Enabled _ADLY_PD 1 Powerdown X_Y 0_1 1 X_Y 2_3 1 X_Y 4_5 0 Powerdown the clock group defined by X and Y 3 CLKoutX_Y_PD X_Y 6_7 0 0 Enabled X_Y 8_9 0 1 Powerdown X_Y 10_11 0 X_Y 12_13 1 Configures the output state of the SYSREF Field Value Disable Mode 0 0x00 Active in normal...

Page 60: ...at 0 0x00 Powerdown 1 0x01 LVDS 2 0x02 HSDS 6 mA 6 4 SDCLKoutY_FMT 0 3 0x03 HSDS 8 mA 4 0x04 HSDS 10 mA 5 0x05 LVPECL 1600 mV 6 0x06 LVPECL 2000 mV 7 0x07 LCPECL Sets the polarity of the device clocks from the DCLKoutX outputs 3 DCLKoutX_POL 0 0 Normal 1 Inverted Sets the output format of the device clocks Field Value Output Format LMK04821 0 0 0x00 Powerdown LMK04826B LMK04828B 1 0x01 LVDS X 0 0 ...

Page 61: ...x03 Reserved Select the source for OSCout 4 OSCout_MUX 0 0 Buffered OSCin 1 Feedback Mux Selects the output format of OSCout When powered down these pins may be used as CLKin2 Field Value OSCout Format 0 0x00 Powerdown CLKin2 1 0x01 LVDS 2 0x02 Reserved 3 0x03 Reserved 4 0x04 LVPECL 1600 mVpp 5 0x05 LVPECL 2000 mVpp 3 0 OSCout_FMT 4 6 0x06 LVCMOS Norm Inv 7 0x07 LVCMOS Inv Norm 8 0x08 LVCMOS Norm ...

Page 62: ...LT 7 3 NA 0 Reserved Selects the SYSREF output from SYSREF_MUX or CLKin0 direct Field Value SYSREF Source SYSREF_ 2 0 CLKin0_MUX 0 SYSREF Mux 1 CLKin0 Direct from CLKin0_OUT_MUX Selects the SYSREF source Field Value SYSREF Source 0 0x00 Normal SYNC 1 0 SYSREF_MUX 0 1 0x01 Re clocked 2 0x02 SYSREF Pulser 3 0x03 SYSREF Continuous 62 Submit Documentation Feedback Copyright 2013 2015 Texas Instruments...

Page 63: ...SREF_DIV 7 0 0 8190 0x1FFE 8190 8191 0X1FFF 8191 9 7 3 4 SYSREF_DDLY 12 8 SYSREF_DDLY 7 0 These registers set the delay of the SYSREF digital delay value Table 26 SYSREF Digital Delay Register Configuration SYSREF_DDLY 12 0 MSB LSB 0x13C 4 0 0x13D 7 0 POR BIT REGISTERS NAME DESCRIPTION DEFAULT 7 5 0x13C NA 0 Reserved Sets the value of the SYSREF digital delay Field Value Delay Value 4 0 0x13C SYSR...

Page 64: ... 1 0 SYSREF_PULSE_CNT 3 1 0x01 2 pulses 2 0x02 4 pulses 3 0x03 8 pulses 9 7 3 6 PLL2_NCLK_MUX PLL1_NCLK_MUX FB_MUX FB_MUX_EN This register controls the feedback feature Table 28 Register 0x13F POR BIT NAME DESCRIPTION DEFAULT 7 5 NA 0 Reserved Selects the input to the PLL2 N Divider 4 PLL2_NCLK_MUX 0 0 PLL Prescaler 1 Feedback Mux Selects the input to the PLL1 N Delay 3 PLL1_NCLK_MUX 0 0 OSCin 1 F...

Page 65: ...d by individual SYSREF output registers 1 Powerdown Powerdown the SYSREF digital delay circuitry 0 Normal operation SYSREF digital delay may be used Must be powered up during 1 SYSREF_DDLY_PD 1 SYNC for deterministic phase relationship with other clocks 1 Powerdown Powerdown the SYSREF pulse generator 0 SYSREF_PLSR_PD 1 0 Normal operation 1 Powerdown 9 7 3 8 DDLYdSYSREF_EN DDLYdX_EN This register ...

Page 66: ...c digital delay can only be started by SPI Other registers must be set SYNC_MODE 3 Table 31 Register 0x142 POR BIT NAME DESCRIPTION DEFAULT 7 4 NA 0 Reserved Sets the number of dynamic digital delay adjustments that will occur Field Value SYNC Generation 0 0x00 No Adjust 1 0x01 1 step 3 0 DDLYd_STEP_CNT 0 2 0x02 2 steps 3 0x03 3 steps 14 0x0E 14 steps 15 0x0F 15 steps 66 Submit Documentation Feedb...

Page 67: ...s in the clock being held in SYNC for a minimum amount of time Sets the polarity of the SYNC pin 5 SYNC_POL 0 0 Normal 1 Inverted Enables the SYNC functionality 4 SYNC_EN 1 0 Disabled 1 Enabled 0 Off 3 SYNC_PLL2_DLD 0 1 Assert SYNC until PLL2 DLD 1 0 Off 2 SYNC_PLL1_DLD 0 1 Assert SYNC until PLL1 DLD 1 Sets the method of generating a SYNC event Field Value SYNC Generation Prevent SYNC Pin SYNC_PLL...

Page 68: ...egister to value 127 Table 34 Register 0x145 POR BIT NAME DESCRIPTION DEFAULT 7 0 Fixed Register 0 Always program to 127 Always program this register to value 170 Table 35 Register 0x171 POR BIT NAME DESCRIPTION DEFAULT 7 0 Fixed Register 10 0x0A Always program to 170 0xAA Always program this register to value 2 Table 36 Register 0x172 POR BIT NAME DESCRIPTION DEFAULT 7 0 Fixed Register 0 Always p...

Page 69: ...d input must AC grounded 9 7 4 2 CLKin_SEL_POL CLKin_SEL_MODE CLKin1_OUT_MUX CLKin0_OUT_MUX Table 38 Register 0x147 POR BIT NAME DESCRIPTION DEFAULT Inverts the CLKin polarity for use in pin select mode 7 CLKin_SEL_POL 0 0 Active High 1 Active Low Sets the mode used in determining the reference for PLL1 Field Value CLKin Mode 0 0x00 CLKin0 Manual 1 0x01 CLKin1 Manual 2 0x02 CLKin2 Manual 6 4 CLKin...

Page 70: ..._MUX 0 3 0x03 DAC Locked 4 0x04 DAC Low 5 0x05 DAC High 6 0x06 SPI Readback 7 0x07 Reserved This sets the IO type of the CLKin_SEL0 pin Field Value Configuration Function 0 0x00 Input Input mode see Input Clock Switching Pin 1 0x01 Input w pull up resistor Select Mode for 2 0 CLKin_SEL0_TYPE 2 2 0x02 Input w pull down resistor description of input mode 3 0x03 Output push pull Output modes the 4 0x...

Page 71: ... Output Format 0 0x00 Logic Low 1 0x01 CLKin1 LOS 2 0x02 CLKin1 Selected 5 3 CLKin_SEL1_MUX 0 3 0x03 DAC Locked 4 0x04 DAC Low 5 0x05 DAC High 6 0x06 SPI Readback 7 0x07 Reserved This sets the IO type of the CLKin_SEL1 pin Field Value Configuration Function 0 0x00 Input Input mode see Input Clock 1 0x01 Input w pull up resistor Switching Pin Select Mode for description of input mode 2 0 CLKin_SEL1...

Page 72: ...3 RESET_MUX 0 2 0x02 CLKin2 Selected 3 0x03 DAC Locked 4 0x04 DAC Low 5 0x05 DAC High 6 0x06 SPI Readback This sets the IO type of the RESET pin Field Value Configuration Function 0 0x00 Input Reset Mode 1 0x01 Input w pull up resistor Reset pin high Reset 2 0 RESET_TYPE 2 2 0x02 Input w pull down resistor 3 0x03 Output push pull Output modes see the 4 0x04 Output inverted push pull RESET_MUX regi...

Page 73: ... Enable the DAC to track the PLL1 tuning voltage optionally for use in holdover mode After device reset tracking starts at DAC code 512 4 TRACK_EN 1 Tracking can be used to monitor PLL1 voltage in any mode 0 Disabled 1 Enabled will only track when PLL1 is locked This bit forces holdover mode When holdover mode is forced if MAN_DAC_EN 1 then the DAC will set the programmed MAN_DAC value Otherwise t...

Page 74: ...alue 1 0 0x14B MAN_DAC 9 8 2 0 0x00 0 1 0x01 1 2 0x02 2 7 0 0x14C MAN_DAC 7 0 0 1022 0x3FE 1022 1023 0x3FF 1023 9 7 6 3 DAC_TRIP_LOW This register contains the high value at which holdover mode is entered Table 44 Register 0x14D POR BIT NAME DESCRIPTION DEFAULT 7 6 NA 0 Reserved Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET is enabled Field Value DAC Trip Value 0 0x00 1 x Vcc...

Page 75: ...red if HOLDOVER_VTUNE_DET is enabled Field Value DAC Trip Value 0 0x00 1 x Vcc 64 1 0x01 2 x Vcc 64 2 0x02 3 x Vcc 64 5 0 DAC_TRIP_HIGH 0 3 0x03 4 x Vcc 64 61 0x17 62 x Vcc 64 62 0x18 63 x Vcc 64 63 0x19 64 x Vcc 64 9 7 6 5 DAC_CLK_CNTR This register contains the value of the DAC when in tracked mode Table 46 Register 0x14F POR BIT NAME DESCRIPTION DEFAULT This with DAC_CLK_MULT set the rate at wh...

Page 76: ... Vtune rail detections When the DAC achieves a specified Vtune if this bit is enabled the current clock input is considered invalid and an input clock switch event HOLDOVER 2 0 is generated _VTUNE_DET 0 Disabled 1 Enabled HOLDOVER Determines whether a clock switch event will enter holdover use hitless switching 1 _HITLESS 1 0 Hard Switch _SWITCH 1 Hitless switching has an undefined switch time Set...

Page 77: ...1 2 0x02 2 7 0 0x154 CLKin0_R 7 0 120 16382 0x3FFE 16382 16383 0x3FFF 16383 9 7 7 2 CLKin1_R 13 8 CLKin1_R 7 0 Table 51 CLKin1_R 13 0 MSB LSB 0x155 5 0 0x156 7 0 These registers contain the value of the CLKin1 R divider Table 52 Registers 0x155 and 0x156 POR BIT REGISTERS NAME DESCRIPTION DEFAULT 7 6 0x155 NA 0 Reserved The value of PLL1 N counter when CLKin1 is selected Field Value Divide Value 5...

Page 78: ...0x158 CLKin2_R 7 0 150 16382 0x3FFE 16382 16383 0x3FFF 16383 9 7 7 4 PLL1_N Table 54 PLL1_N 13 8 PLL1_N 7 0 PLL1_N 13 0 MSB LSB 0x159 5 0 0x15A 7 0 These registers contain the N divider value for PLL1 Table 55 Registers 0x159 and 0x15A POR BIT REGISTERS NAME DESCRIPTION DEFAULT 7 6 0x159 NA 0 Reserved The value of PLL1 N counter Field Value Divide Value 5 0 0x159 PLL1_N 13 8 0 0 0x00 Not Valid 1 0...

Page 79: ...the PLL1 charge pump output pin CPout1 to be placed into TRI STATE 5 PLL1_CP_TRI 0 0 PLL1 CPout1 is active 1 PLL1 CPout1 is at TRI STATE PLL1_CP_POL sets the charge pump polarity for PLL1 Many VCXOs use positive slope A positive slope VCXO increases output frequency with increasing voltage A negative 4 PLL1_CP_POL 1 slope VCXO decreases output frequency with increasing voltage 0 Negative Slope VCO...

Page 80: ...N 7 6 0x15C NA 0 Reserved The reference and feedback of PLL1 must be within the window of phase error as specified by PLL1_WND_SIZE for this many phase detector cycles before PLL1 digital lock detect is asserted PLL1_DLD 5 0 0x15C 32 Field Value Delay Value _CNT 13 8 0 0x00 Reserved 1 0x01 1 2 0x02 2 3 0x03 3 PLL1_DLD 7 0 0x15D 0 _CNT 7 0 16 382 0x3FFE 16 382 16 383 0x3FFF 16 383 80 Submit Documen...

Page 81: ... delay mode Field Value Gain 0 0x00 0 ps 1 0x01 205 ps 2 0x02 410 ps 5 3 PLL1_R_DLY 0 3 0x03 615 ps 4 0x04 820 ps 5 0x05 1025 ps 6 0x06 1230 ps 7 0x07 1435 ps Increasing delay of PLL1_N_DLY will cause the outputs to lead from CLKinX For use in 0 delay mode Field Value Gain 0 0x00 0 ps 1 0x01 205 ps 2 0x02 410 ps 2 0 PLL1_N_DLY 0 3 0x03 615 ps 4 0x04 820 ps 5 0x05 1025 ps 6 0x06 1230 ps 7 0x07 1435...

Page 82: ...ack 7 3 PLL1_LD_MUX 1 8 0x08 DAC Rail 9 0x09 DAC Low 10 0x0A DAC High 11 0x0B PLL1_N 12 0x0C PLL1_N 2 13 0x0D PLL2_N 14 0x0E PLL2_N 2 15 0x0F PLL1_R 16 0x10 PLL1_R 2 17 0x11 PLL2_R 1 18 0x12 PLL2_R 2 1 Sets the IO type of the Status_LD1 pin Field Value TYPE 0 0x00 Reserved 1 0x01 Reserved 2 0 PLL1_LD_TYPE 6 2 0x02 Reserved 3 0x03 Output push pull 4 0x04 Output inverted push pull 5 0x05 Reserved 6 ...

Page 83: ...e PLL2 R divider Table 62 Registers 0x160 and 0x161 BIT REGISTERS NAME POR DEFAULT DESCRIPTION 7 4 0x160 NA 0 Reserved Valid values for the PLL2 R divider Field Value Divide Value 3 0 0x160 PLL2_R 11 8 0 0 0x00 Not Valid 1 0x01 1 2 0x02 2 3 0x03 3 7 0 0x161 PLL2_R 7 0 2 4 094 0xFFE 4 094 4 095 0xFFF 4 095 Copyright 2013 2015 Texas Instruments Incorporated Submit Documentation Feedback 83 Product F...

Page 84: ...n Frequency 0 0x00 0 to 63 MHz 4 2 OSCin_FREQ 7 1 0x01 63 MHz to 127 MHz 2 0x02 127 MHz to 255 MHz 3 0x03 Reserved 4 0x04 255 MHz to 500 MHz 5 0x05 to 7 0x07 Reserved If an external crystal is being used to implement a discrete VCXO the internal feedback amplifier must be enabled with this bit in order to complete the oscillator circuit 1 PLL2_XTAL_EN 0 0 Oscillator Amplifier Disabled 1 Oscillator...

Page 85: ... 15 8 0 2 0x02 2 7 0 0x165 PLL2_N_CAL 7 0 12 262 143 0x3FFFF 262 143 9 7 8 4 PLL2_FCAL_DIS PLL2_N This register disables frequency calibration and sets the PLL2 N divider value Programming register 0x168 starts a VCO calibration routine if PLL2_FCAL_DIS 0 Table 66 PLL2_N 17 0 MSB LSB 0x166 1 0 0x167 7 0 0x168 7 0 Table 67 Registers 0x166 0x167 and 0x168 POR BIT REGISTERS NAME DESCRIPTION DEFAULT 7...

Page 86: ...w also illustrates the impact of the PLL2 TRISTATE bit in conjunction with PLL2_CP_GAIN Field Value Definition 0 0x00 100 µA 4 3 PLL2_CP_GAIN 3 1 0x01 400 µA 2 0x02 1600 µA 3 0x03 3200 µA PLL2_CP_POL sets the charge pump polarity for PLL2 The internal VCO requires the negative charge pump polarity to be selected Many VCOs use positive slope A positive slope VCO increases output frequency with incr...

Page 87: ...or 6 0x16A SYSREF_REQ_EN 0 continuous pulses When using this feature enable pulser and set SYSREF_MUX 2 Pulser The reference and feedback of PLL2 must be within the window of phase error as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles before PLL2 digital lock detect is asserted PLL2_DLD 5 0 0x16A 32 Field Value Divide Value _CNT 13 8 0 0x00 Not Valid 1 0x01 1 2 0x02 2 3 0x03 3 7 0 0x16B PLL2...

Page 88: ...g table Field Value Resistance 0 0x00 200 Ω 1 0x01 1 kΩ 5 3 PLL2_LF_R4 0 2 0x02 2 kΩ 3 0x03 4 kΩ 4 0x04 16 kΩ 5 0x05 Reserved 6 0x06 Reserved 7 0x07 Reserved Internal loop filter components are available for PLL2 enabling either 3rd or 4th order loop filters without requiring external components Internal loop filter resistor R3 can be set according to the following table Field Value Resistance 0 0...

Page 89: ...C4 0 6 0x06 66 pF 7 0x07 71 pF 8 0x08 103 pF 9 0x09 108 pF 10 0x0A 122 pF 11 0x0B 126 pF 12 0x0C 141 pF 13 0x0D 146 pF 14 0x0E Reserved 15 0x0F Reserved Internal loop filter components are available for PLL2 enabling either 3rd or 4th order loop filters without requiring external components Internal loop filter capacitor C3 can be set according to the following table Field Value Resistance 0 0x00 ...

Page 90: ...PI Readback 7 3 PLL2_LD_MUX 2 8 0x08 DAC Rail 9 0x09 DAC Low 10 0x0A DAC High 11 0x0B PLL1_N 12 0x0C PLL1_N 2 13 0x0D PLL2_N 14 0x0E PLL2_N 2 15 0x0F PLL1_R 16 0x10 PLL1_R 2 17 0x11 PLL2_R 1 18 0x12 PLL2_R 2 1 Sets the IO type of the Status_LD2 pin Field Value TYPE 0 0x00 Reserved 1 0x01 Reserved 2 0 PLL2_LD_TYPE 6 2 0x02 Reserved 3 0x03 Output push pull 4 0x04 Output inverted push pull 5 0x05 Res...

Page 91: ...O1 for LMK04821 the clock distribution frequency will be equal to VCO1 frequency divided by this divide value Note this divider is also on the PLL2 feedback path and will impact PLL2 N divider value Unlisted field values are reserved Field Value Divide Value 0 0x00 2 VCO1_DIV 4 0 0 5 0x05 3 LMK04821 only 10 0x0A 8 20 0x14 4 23 0x17 5 27 0x1B 7 30 0x1E 6 9 7 9 3 OPT_REG_1 This register must be writ...

Page 92: ...LOST with 1 and then 0 0 RB_PLL1_LD_LOST will be set on next falling PLL1 DLD edge 0 CLR_PLL1_LD_LOST 1 RB_PLL1_LD_LOST is held clear 0 User must clear this bit to allow RB_PLL1_LD_LOST to become set again 9 7 9 6 RB_PLL2_LD_LOST RB_PLL2_LD CLR_PLL2_LD_LOST Table 79 Register 0x0x183 BIT NAME DESCRIPTION 7 3 N A Reserved 2 RB_PLL2_LD_LOST This is set when PLL2 DLD edge falls Does not set if cleared...

Page 93: ..._CLKin0_SEL Read back 1 CLKin0 is selected for input to PLL1 2 N A Read back 1 CLKin1 LOS is active 1 RB_CLKin1_LOS Read back 0 CLKin1 LOS is not active Read back 1 CLKin0 LOS is active 0 RB_CLKin0_LOS Read back 0 CLKin0 LOS is not active 9 7 9 8 RB_DAC_VALUE Contains the value of the DAC for user readback FIELD NAME MSB LSB RB_DAC_VALUE 0x184 7 6 0x185 7 0 Table 81 Registers 0x184 and 0x185 POR B...

Page 94: ... 0x1FFD 7 0 0x1FFE 7 0 0x1FFF 7 0 Table 83 Registers 0x1FFD 0x1FFE and 0x1FFF POR BIT REGISTERS NAME DESCRIPTION DEFAULT 0 Registers unlocked 7 0 0x1FFD SPI_LOCK 23 16 0 1 to 255 Registers locked 0 Registers unlocked 7 0 0x1FFE SPI_LOCK 15 8 0 1 to 255 Registers locked 0 to 82 Registers locked 7 0 0x1FFF SPI_LOCK 7 0 83 83 Registers unlocked 84 to 256 Registers locked 94 Submit Documentation Feedb...

Page 95: ...al lock detect event to occur there must be a lock count number of phase detector cycles of PLLX during which the time phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable window size Since there must be at least lock count phase detector events before a lock event occurs a minimum digital lock event time can be calculated as lock count fPDX where X...

Page 96: ...nce clocks The LMK0482x family internally biases the input pins so the differential interface should be AC coupled The recommended circuits for driving the CLKin pins with either LVDS or LVPECL are shown in Figure 20 and Figure 21 Figure 20 CLKinX X Termination for an LVDS Reference Clock Source Figure 21 CLKinX X Termination for an LVPECL Reference Clock Source Finally a reference clock source th...

Page 97: ...CLKinX X Single ended Termination If the CLKin pins are being driven with a single ended LVCMOS LVTTL source either DC coupling or AC coupling may be used If DC coupling is used the CLKinX_BUF_TYPE should be set to MOS buffer mode CLKinX_BUF_TYPE 1 and the voltage swing of the source must meet the specifications for DC coupled MOS mode clock inputs given in Electrical Characteristics If AC couplin...

Page 98: ...VCO0 offers lower noise floor while VCO1 offers improved VCO phase noise which reduces RMS jitter Depending on application requirements and simulations one solution may be chosen over the other In this case we will choose LMK04828B_VCO1 for improved RMS jitter in the 12 kHz to 20 MHz integration range Larger integration ranges may benefit from the lower noise floor of VCO0 10 2 3 2 1 1 Clock Archi...

Page 99: ...the DCLKoutX output then turn on the paired SDCLKoutY output for SYSREF output For Non JESD204B outputs both DCLKoutX and paired SDCLKoutY may be driven by the device clock divider to maximize number of available outputs Frequency planning for assignment of outputs To minimize crosstalk perform frequency planning CLKout assignments to keep common frequencies on outputs close together It is best to...

Page 100: ... Ω emitter resistors DCLKout0_1_IDL 1 DCLKout0_1_ODL 1 DCLKout2_3_IDL 1 DCLKout2_3_ODL 1 Figure 27 DCLKout4 983 04 MHz Figure 28 DCLKout6 983 04 MHz LVPECL16 w 240 Ω emitter resistors LVPECL16 w 240 Ω emitter resistors DCLKout0_1_IDL 1 DCLKout0_1_ODL 0 DCLKout0_1_IDL 1 DCLKout0_1_ODL 0 100 Submit Documentation Feedback Copyright 2013 2015 Texas Instruments Incorporated Product Folder Links LMK0482...

Page 101: ...t VCXO Measurement Normal output measured Inverse 50 Ω termination Open loop holdover mode set 10 3 Do s and Don ts 10 3 1 Pin Connection Recommendations VCC Pins and Decoupling all VCC pins must always be connected Unused Clock Outputs leave unused clock outputs floating and powered down Unused Clock Inputs unused clock inputs can be left floating Copyright 2013 2015 Texas Instruments Incorporate...

Page 102: ...e TRACK_EN 1 2 5 8 25 SYNC_EN 1 Required for SYNC and SYSREF functionality 7 6 25 08 Enabled SYSREF_PD 0 27 2 89 76 Dynamic Digital Delay SYSREF_DDLY_PD 0 5 16 5 enabled SYSREF Pulser is enabled SYSREF_PLSR_PD 0 4 1 13 53 SYSREF Pulses mode SYSREF_MUX 2 3 9 9 SYSREF Continuous SYSREF_MUX 3 3 9 9 mode CLOCK GROUP Enabled Any one of the CLKoutX_Y_PD 0 20 1 66 33 IDL Any one of the CLKoutX_Y_IDL 1 2 ...

Page 103: ...nsumption times RθJA should not exceed 125 C The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to a printed circuit board To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package The exposed pad...

Page 104: ...rge pump output shorter traces are better Place a resistors and caps closer to IC except for a single capac and associated resistor if any next to VCXO In a 2nd o filter place C1 close to VCXO Vtune pin In a 3rd and 4th order filter place R3 C3 or R4 C4 respectively close to VCXO CLKouts OSCouts Normally differential signals shoul routed tightly coupled to minimize PCB crosstalk Trace impedance an...

Page 105: ...ARE COMMUNITY LMK04821 Click here Click here Click here Click here Click here LMK04826 Click here Click here Click here Click here Click here LMK04828 Click here Click here Click here Click here Click here 13 3 Trademarks PLLatinum is a trademark of Texas Instruments All other trademarks are the property of their respective owners 13 4 Electrostatic Discharge Caution These devices have limited bui...

Page 106: ...vice will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 RoHS TI defines RoHS to mean se...

Page 107: ... bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on in...

Page 108: ...Q1 LMK04826BISQ NOPB WQFN NKD 64 1000 330 0 16 4 9 3 9 3 1 3 12 0 16 0 Q1 LMK04826BISQE NOPB WQFN NKD 64 250 178 0 16 4 9 3 9 3 1 3 12 0 16 0 Q1 LMK04826BISQX NOPB WQFN NKD 64 2000 330 0 16 4 9 3 9 3 1 3 12 0 16 0 Q1 LMK04828BISQ NOPB WQFN NKD 64 1000 330 0 16 4 9 3 9 3 1 3 12 0 16 0 Q1 LMK04828BISQE NOPB WQFN NKD 64 250 178 0 16 4 9 3 9 3 1 3 12 0 16 0 Q1 LMK04828BISQX NOPB WQFN NKD 64 2000 330 0...

Page 109: ...5 0 LMK04826BISQ NOPB WQFN NKD 64 1000 367 0 367 0 38 0 LMK04826BISQE NOPB WQFN NKD 64 250 210 0 185 0 35 0 LMK04826BISQX NOPB WQFN NKD 64 2000 367 0 367 0 38 0 LMK04828BISQ NOPB WQFN NKD 64 1000 367 0 367 0 38 0 LMK04828BISQE NOPB WQFN NKD 64 250 210 0 185 0 35 0 LMK04828BISQX NOPB WQFN NKD 64 2000 367 0 367 0 38 0 PACKAGE MATERIALS INFORMATION www ti com 15 Sep 2018 Pack Materials Page 2 ...

Page 110: ...3 48 17 32 64 49 OPTIONAL PIN 1 ID SEE TERMINAL DETAIL NOTES 1 All linear dimensions are in millimeters Dimensions in parenthesis are for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change without notice 3 The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance 0 1 C A B 0 05 C SCALE 1 600 DETAIL OPTI...

Page 111: ...4A WQFN SYMM SEE DETAILS 1 16 17 32 33 48 49 64 SYMM LAND PATTERN EXAMPLE SCALE 8X NOTES continued 4 This package is designed to be soldered to a thermal pad on the board For more information refer to QFN SON PCB application note in literature No SLUA271 www ti com lit slua271 SOLDER MASK OPENING METAL SOLDER MASK DEFINED METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED PREFER...

Page 112: ...ht NKD0064A WQFN NOTES continued 5 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release IPC 7525 may have alternate design recommendations SYMM METAL TYP SOLDERPASTE EXAMPLE BASED ON 0 125mm THICK STENCIL EXPOSED PAD 65 PRINTED SOLDER COVERAGE BY AREA SCALE 10X 1 16 17 32 33 48 49 64 SYMM ...

Page 113: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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