Quick Start
3
SNLU098A – March 2012 – Revised July 2019
Copyright © 2012–2019, Texas Instruments Incorporated
LMK00101 User’s Guide
2.1
Quick Start Description
The LMK00101 EVK allows full verification of the device functionality and performance specifications. To
quickly set up and operate the board with basic equipment, refer to the quick start procedure below and
test setup shown in
.
1. Verify the output mode control switches, S1[1:4], match the states shown in
to reflect the
default output clock interfaces configured on the EVK.
Table 2. Default Clock Output Modes / Interfaces
SW POSITION/NAME
SW STATE
S1[1] / SEL1
0 (OFF)
S1[2] / SEL0
1 (ON)
S1[3] / OE
1 (OFF)
S1[4] / NC
Unused
2. Connect the Vdd SMA from the board to a 3.3 V source. This powers the non-output portions of the
LMK00101.
3. Connect the Vdd CLKout SMA from the board to a 3.3 V source. This powers the output drivers of the
LMK00101.
4. Set the desired clock input using the input selection control switches, S1[1:2], per Table 3. A
differential clock source can be connected to SMAs
CLKin0/0*
or
CLKin1/1*
.
Note: CLKin0/0* and CLKin1/1* paths are configured by default to receive a differential clock as the
input. The SMA inputs are DC coupled to the device inputs and terminated with 100
Ω
differential.
Refer to the Clock Inputs section to configure the EVK for a single-ended input.
Table 3. Input Selection (0=SW OFF, 1=SW ON)
SELECTED INPUT
DEFAULT INPUT MODE
S1[1]CLKin_Sel0 State
S1[2] CLKin_Sel1 State
CLKin0/0*
Differential clock
0
0
CLKin1/1*
Differential clock
0
1
OSCin
Select OSCin
1
Don't Care
5. Connect and measure any clock output SMA labeled
CLKoutX
to an oscilloscope or other test
instrument using SMA cable(s). The output clock will be level-translated/buffered copy of the selected
clock input or crystal oscillator. Note: All output clocks are AC-coupled to the SMA connectors to
ensure safe use with RF instruments.
Note: Switching noise from one or more un-terminated outputs may impair the signal quality of the
measured output(s). To minimize switching noise and EMI, properly terminate any unused output path
using an SMA load or the component options near the SMA outputs, or alternatively, remove the 0
Ω
series resistor nearest the unused output pin.
3
Signal Path and Control Switches
The LMK00101 supports single-ended or differential clocks on CLKin0 and CLKin1. A third input, OSCin,
has an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an
external single-ended clock. The three-input multiplexer is pin-controlled. To achieve the maximum
operating frequency and lowest additive jitter, it is recommended to use a differential clock with high input
slew rate (>1 V/ns) and DC-coupling to either CLKin0 or CLKin1 port.
All control pins are configured with the control switch, S3. The output enable logic is shown in
Table 4. Output Enable Selection (0=OFF, 1=ON)
CLKout ENABLE MODE
S1[3]-OE
Disabled/Hi-Z
0
Enabled
1
