Texas Instruments LM8365, User Manual, Page: 6 / 18

Programmed Delay with 0.1 µF Capacitor
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3 Programmed Delay with 0.1 µF Capacitor
A typical application usually requires a certain delay before the microprocessor is pulled out of reset once
the VCC rises above its minimum operating voltage. This is to allow some time for the VCC to settle to a
stable voltage before the microprocessor begins running.
Figure 3 shows this delay, which is programmed
by populating J2. This corresponds to a CD capacitor of 0.1 µF. In an application, this provides the user
confidence that the microprocessor will exit its reset state when its VCC has stabilized above the minimum
operating voltage.
Figure 3. 0.1 µF Capacitor Programmed Delay
6 Applications SNVU493 – October 2015
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