Texas Instruments LM5064EVK, User Manual, Page: 15 / 28

VCC
UVLO/
EN
OVLO
VEE
R1
R2
R3
2.48V
20
P
A
2.47V
21
P
A
TIMER AND GATE
LOGIC CONTROL
LM5064
R4/3a
R2a
GND
V
SYS
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UVLO and OVLO Input Voltage Threshold
15 SNVA481B – October 2011 – Revised January 2020
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AN-2143 LM5064 Evaluation Kit
The waveform at the TIMER pin can be monitored at the TIMER test point. On this evaluation board, the
initial fault time-out period is 8 ms and the restart time is 1.4 seconds.
14 UVLO and OVLO Input Voltage Threshold
Programming the UVLO threshold sets the minimum system voltage to enable Q1. If VCC-VEE is below
the UVLO thresholds, Q1 is switched off, denying power to the load. Programmable hysteresis is
adjustable by changing the value of R1.
The UVLO threshold is set with two resistors (R1, R2) as shown in Figure 14 and an internal 20 µA
current source allows a hysteresis voltage to be set.
The OVLO threshold sets the maximum voltage that can be present on the input before the device turns
off the series pass device. The OVLO threshold is set with the two resistors (R3, R4). The hysterisis
voltage is set by the internal 21 uA current source and the value of R3.
Figure 14. Programming the UVLO and OVLO Thresholds
15 Shutdown
With the circuit in normal operation, the LM5064 can be shutdown by pulling the UVLO/EN pin to VEE or
by clicking the ON/OFF button on the LM5064 block representation in the GUI.
16 Board Layout and Probing Cautions
Refer to the product datasheet for detailed layout guidelines. For most applications the layout of this
evaluation module as detailed in the PC Board Layout section of this document should be sufficient to
provide a working solution with accurate telemetry. The following should be kept in mind when the board is
powered:
1. Use CAUTION when probing the circuit to prevent injury as well as possible damage to the circuit.
2. At maximum load current ( typically 16.7A), the wire size and length used to connect the power source
and the load become very important. The wires connecting this evaluation board to the power source
should be a heavy gauge and twisted together to minimize input inductance. The same applies for the
wires connecting this board to the load. This recommendation is made in order to minimize high
voltage transients from occurring when the load current is shut off.
3. A 60V TVS diode located close to the LM5064EVK GND1 and VEE pins provides the critical function
of clamping inevitable input voltage overshoot when Q
1
turns off at high currents. If operation above
60V is required, the TVS will need to be replaced with a TVS rated at a higher standoff voltage. Always
verify the TVS by performing a worst-case current limit at the maximum input voltage and monitoring
the resulting input voltage surge. The TVS should be able to clamp the input below 100V in all cases.
4. The VEE points for the UVLO/EN and OVLO resistor networks are tied directly to a via where the