Texas Instruments LAUNCHXL-F280025C, Schematic Diagrams, Page: 3 / 8

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MCU089A_AltRouting_Misc.SchDoc
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LAUNCHXL-F280025C Project Title:
Designed for: Public Release
Assembly Variant: 001
© Texas Instruments 2020
Drawn By:
Engineer:
Kevin Allen
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or i t s
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Not in version control SVN Rev:
MCU089 Number: Rev: A
TID #: N/A
Orderable: LAUNCHXL-F280025C
1A
1
GND
2
2A
3
2Y
4
VCC
5
1Y
6
U7
SN74LVC2G07DBVR
GND
GND
GPIO31
GPIO34
10M
R31
+3V3
+3V3
Red
2
1
LED4
Green
1
2
LED5
+3V3
User LEDs
10M
R30
0.1uF
C44
0
R34
0
R35
EQEP Level Shifter
To disable the Level Shifter:
1. De-populate R53
2. Place a 2.2k ohm resistor on R48 to pull-up OE
GPIO6_BP GPIO6_FSITXD0
GPIO7_BP
GPIO12_BP GPIO12_FSIRXD0
GPIO13_BP
GPIO33_BP
GPIO33_CANRX
GPIO32_BP
GPIO32_CANTX
GPIO32
Boot Mode Select
GPIO13_FSIRXCLK
GPIO33
FSI Routing
0
R44
0
R50
0
R49
0
R45
GPIO7_FSITXCLK
If needed, depopulate the resistors to isolate the BP headers
from the FSI Headers. By default all are populated.
FSI routing will be as clean as possible to FSI header. BP
resistors will be branches with short stubs off of main branch t o
reduce noise on high speed lines
2
1
5
3
4
6
S4
15pF
C41
15pF
C42
GND
GND GND
Oscillator
By default:
- Crystal Y2 is connected between GPIO18_X2 and
GPIO19_X1.
- GPIO18_BP AND GPIO19_BP are connected to the
BoosterPack headers.
If GPIO18 and GPIO 19 are needed at the Boosterpac k
Headers:
- Remove R32 and R33, populate R36 and R37 with 0 ohm
resistors
- The F28002x device's internal oscillator will need to be used
Route cleanly and place near U1
GPIO44
GPIO44_Q1A
GPIO44_BP
GPIO37
GPIO43
GPIO43_Q1I
GPIO43_BP
3
1
2
6
4
5
S5
GND
+3V3
GND GND
+3V3
QEP1_SEL
QEP1_SEL
GPIO14
GPIO25
GPIO26
GND GND
+3V3
QEP2_SEL
QEP2_SEL
GPIO25_Q2B
GPIO25_BP
GPIO26_Q2I
GPIO26_BP
GPIO14_Q2A
GPIO14_BP
GPIO37_Q1B
GPIO37_BP
S5 (1, UP): QEP signals are routed to the BoosterPac k
Headers (default)
S5 (0, DOWN): QEP signals are routed to the QEP
Headers
i
FSIRX
i
FSIRX
i
FSITX
i
FSITX
Mode #
00
01
02
03
GPIO24 GPIO32 Boot Mode
0
0
0
0
1
1
1
1
Boot from Parallel GPIO
Boot from SCI / Wait Mode
Boot from CAN
Boot from Flash
Selected Boot Mode Chart
680
R29
680
R28
EQEP Routing
1 3
4 2
G G
Y2
+3V3
GPIO41_FSIRXD1
0
R55
0
R54
GPIO41_BP
GPIO46_BP
i
FSITX
i
FSIRX
GPIO46_FSITXD1
BP BP
J12 J13
GPIO18_X2 GPIO19_X1
GPIO18_BP GPIO19_BP
XTAL_X1 XTAL_X2
3
1
2
6
4
5
S3
SPDT
GPIO24 GPIO32
+3V3
GND
+5V0
+3V3
GND
GND GND
GPIO44_Q1A
GPIO37_Q1B
GPIO43_Q1I
GPIO14_Q2A
GPIO25_Q2B
GPIO26_Q2I
EQEP2A
EQEP2B
EQEP2I
EQEP1A
EQEP1B
EQEP1I
0.1uF
C65
0.1uF
C64
VCCA
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
11
GND
12
GND
13
B8
14
B7
15
B6
16
B5
17
B4
18
B3
19
B2
20
B1
21
OE
22
VCCB
23
VCCB
24
SN74LVC8T245PW
U13
1000pF
C67
0
R53
GND
2.2k
R48
GND
+3V3
0
R33
0
R32
0
R36
0
R37
CAN Routing
IN1
1
NO1
2
GND
3
NO2
4
IN2
5
COM2
6
NC2
7
V+
8
NC1
9
COM1
10
TS5A23157DGSR
U6
IN1
1
NO1
2
GND
3
NO2
4
IN2
5
COM2
6
NC2
7
V+
8
NC1
9
COM1
10
TS5A23157DGSR
U8
GPIO29
GPIO17
MCU_TXD
GPIO28_BP
GPIO17_BP
GPIO28
GPIO16
MCU_RXD
GPIO29_BP
GPIO16_BP
GPIO29_SCITX
GPIO16_SCITX
GPIO28_SCIRX
GPIO17_SCIRX
GPIO29_SCITX
GPIO16_SCITX
GPIO17_SCIRX
GPIO28_SCIRX
UART Routing
GND
+3V3
0.1uF
C43
0.1uF
C45
+3V3
GND
3
1
2
6
4
5
S2
+3V3
SCI_SEL1 SCI_SEL2
GND
GND
GND
SCI_SEL1
SCI_SEL1
IN1
1
NO1
2
GND
3
NO2
4
IN2
5
COM2
6
NC2
7
V+
8
NC1
9
COM1
10
TS5A23157DGSR
U9
GND
SCI_SEL1
+3V3
0.1uF
C46
GND SCI_SEL1 SCI_SEL2
SCI_SEL2
VCC
16
1-COM
14
1Y0
12
1Y1
13
2-COM
15
2Y0
2
2Y1
1
3-COM
4
3Y0
5
3Y1
3
A
11
B
10
C
9
INH
6
GND
7
GND
8
SN74LV4053APWR
U11
VCC
16
1-COM
14
1Y0
12
1Y1
13
2-COM
15
2Y0
2
2Y1
1
3-COM
4
3Y0
5
3Y1
3
A
11
B
10
C
9
INH
6
GND
7
GND
8
SN74LV4053APWR
U14
0
R46
GPIO8
i
FSITDM
i
FSITDM
0
R51
GPIO10
i
FSITDM
0
R56
GPIO1
SCI_SEL1
0
0
1
1
SCI_SEL2
0
1
0
1
GPIO28/29 Route
XDS110 COM Port
XDS110 COM Port
BP
BP
- DEFAULT
- J1
- J1
- J8
- J8
- J6
- J4
- J1
- J5
- J5
- J1
- J6 J6 -
- J8
- J8
- J5
- J8
- J8
- J6
- J4 J2 -
J6 -
J1 -
J5 - - J6
SPDT
SPDT
DPDT
+3V3
GND
DIR pin tied low through
R52 by default for B to A
direction.
0
R52
0
R47
GPIO22
GPIO23
0
R42
0
R43
J5 -
J2 -
GND
GND
0.1uF
C49
+3V3
1.00k
R40
0.1uF
C47
GPIO22_PWM_DAC
GPIO23_PWM_DAC
1.00k
R41
0.1uF
C48
GND
PWM DAC
0
R81
GPIO16/17 Route
BP
NC
BP
XDS110 COM Port
10.0k
R38
10.0k
R39
6 1
U10A
4 3
U10B
GND
2
VCC
5
U10C