Texas Instruments Jacinto7, User Manual

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Table 2-16. Test Automation Interface Pin Definition [J50] (continued)
Pin # Pin Name Description Dir
28 RESETz EVM Warm Reset (RESETz) Input
29 <open>
30 INT1z EXTINT / GPIO0_0 Input
31 INT2z WKUP_GPIO0_7 Bi-Dir
32 <open>
33 BOOTMODE_RSTz Bootmode Buffer Reset Input
34 GND Ground
35 <open>
Note
In the DIR, column, output is to the test automation controller, input is from the automation controller.
Bi-Dir signals can be configured as either input or output.
Note
The Signal polarity is defined with a trailing 'z' in the Pin Name, which indicates the signal is active
LOW. For example, POWERDOWNz is an active low signal, meaning '0' = EVM is Powered Down, '1'
= EVM is NOT Powered Down.
2.5.5 ADC [J23_CP]
The EVM supports an interface for connecting external peripherals with ADC inputs. A 20-pin, dual row, 2.54-mm
pitch pin header [J23] supports eight (8) input channels to ADC and trigger, and ADC reference signals. See the
EVM schematic for pinout details.
2.5.6 CSI-TX [J10_SOM]
The J7AEP SOM Board in the EVM includes a 40-pin (2x20, 0.5-mm pitch) high speed camera transmit interface
[J10]. The expansion connector supports a single CSI2-TX (4Lane) interface. The interface is designed for
internal testing and may not include all the required power/signals for interfacing with a display. See schematic
for connector pinout details.
2.5.7 Accessory Power Connector [J42_CP]
A power output connector [J42] is provided for conditions where an expansion board requires additional power.
The 2-pin connector (Phoenix 1757242) supplies a regulated 12-V output, up to 5000 mA. Mating connector is
TBD.
Table 2-17. Accessory Power Connector [J42]
Pin # Pin Name Description Dir
1 GND Ground
2 Power Power, 12 V Output
3 Circuit Details
This sections provides additional details on the EVM design and processor connections.
3.1 Top Level Diagram
Figure 3-1 shows the functional block diagram of the EVM Board.
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