Texas Instruments J721EXSOMXEVM User Manual Download Page 31

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J721E EVM Hardware Architecture

SPRUIS4A – December 2019 – Revised May 2020

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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)

4.4

GPIO Mapping

The general purpose I/Os (GPIOs) of the SoC have two major groups: WKUP/MCU and MAIN.

Table 18

describes the detailed GPIO mapping of SoC with EVM peripherals.

Table 18. J721E SoC - GPIO Mapping Table

J721E SoC - GPIO Mapping Table

Package Signal

Name

GPIO

Net name

In/Out

Default

State

Remarks

WKUP/MCU Domain

WKUP_

GPIO0_0

WKUP_

GPIO0_0

MCU_MCAN0_EN

Output

BOOTMODE

Active High

MCU CAN0 Enable

WKUP_

GPIO0_1

WKUP_

GPIO0_1

BOOT_EEPROM_

Output

BOOTMODE

Active High

Boot EEPROM Write protect

WKUP_

GPIO0_2

WKUP_

GPIO0_2

MCU_CAN1_STB

Output

BOOTMODE

Active High

MCU CAN1 Standby

WKUP_

GPIO0_3

WKUP_

GPIO0_3

GPIO_MCU_

RGMII1_RST#

Output

Active low

MCU_RGMII1_Reset

WKUP_

GPIO0_6

WKUP_

GPIO0_6

WKUP_GPIO0_6

I/O

Test Point

Terminated with Test point

WKUP_

GPIO0_7

WKUP_

GPIO0_7

SYS_IRQz

Input

Active low

Push-button Interrupt, User Defined/Wake S2R ('0>1'
- interrupt pending, '1' - normal operation)

WKUP_

GPIO0_8

WKUP_

GPIO0_8

OSPI/HYPER_

MUX_SEL

Output

DIP_SEL

Flash Memory Selection ('0' - OSPI0, '1' - Hyperflash
+ HyperRam)

WKUP_

GPIO0_9

WKUP_

GPIO0_9

PMIC_MCU_INT#

Input

Active low

Interrupt from PMIC

WKUP_

GPIO0_17

WKUP_

GPIO0_17

MCU_OSPI0_

ECC_FAIL

Output

Active High

OSPI_ECC_FAIL (Mux option w/ HYPERBUS_CKn),
MCU_OSPI0_ECC_FAIL is DNI resistor option.

MCU_SPI0_

CLK

WKUP_

GPIO0_52

WKUP_GPIO0_52

I/O

BOOTMODE

Terminated with Test point

MCU_SPI0_

CS0

WKUP_

GPIO0_55

MCU_RGMII1_

INT#

Input

Active Low

MCU Ethernet Interrupt ('0' - interrupt pending, '1' - no
interrupt)

MCU_SPI0_

WKUP_

GPIO0_53

SYS_MCU_

PWRDN

Output

Active low

System Power Down ('0' - normal operation, '1' -
system power down)

MCU_SPI0_

WKUP_

GPIO0_54

MCU_CAN0_STBz

Output

Active low

MCU CAN0 Standby

Main Domain

EXTINTN

GPIO0_0

SOC_EXTINTN

Input

Active low

Push-button Interrupt, User Defined

RGMII6_RX_

CTL

GPIO0_98

C_MCASP10_

AFSR

Active low

I2C0 I/O expander interrupt. ('0' - interrupt pending, '1'
- no interrupt)(I2C0_IOEXP_INT#)
Note: GPIO only available from Trace/GPMC Mux

RGMII6_

RD3

GPIO0_105

IMU_GPIO0

I/O

Used as GPIO0 for IMU Sensor

SPI1_CS1

GPIO0_117

DSI_UB981_INTB

Input

Active low

DSI FPD Link Serializer/Panel Interrupt.
Note: resistor option with CON_DSI0_INT#

UART1_

CTSN

GPIO0_127

GPIO0_127/

EQEP0_S/MLB0_

MLBCLK

Output

Active High

CP Board - MCAN2_STB; GESI -
Boosterpack_GPIO2

UART1_

RTSN

GPIO1_0

GPIO1_0/EQEP0_I

/MLB0_MLBDAT

Output

CP Board - PM I2C Mux seletion. ('0' -
SOC_I2C2_SCL/SDA

→

PM1_SCL/SDA, '1' -

SOC_I2C2_SCL/SDA

→

PM2_SCL/SDA)

GESI - Boosterpack_GPIO1

MCAN1_RX

GPIO1_3

USBC_DIR

Input

USB Type C Cable Orientation. Type-C plug position
2 (H); Type-C plug position 1 (L)

ECAP0_IN_

APWM_

OUT

GPIO1_11

GPIO1_11/MAIN_

I3C0_

SDAPULLEN

Input

Active High

Display I/O expander Interrupt. ('0' - interrupt pending,
'1' - no interrupt) (IOEXP4_INT#)

EXT_

REFCLK1

GPIO1_12

GPIO1_12/MLB0_REFCL

Input

CP Board Audio De-serializer UB926_GPIO1 (Tuner
Unused GPIO)

MMC1_

SDWP

GPIO1_22

ENET_EXP_INTB

Input

Active low

Ethernet Expansion Interrupt. ('0' - interrupt pending,
'1' - no interrupt)

I3C0_SCL

GPIO1_5

H_I3C0_SCL

I/O

CP Board Audio De-serializer UB926_GPIO2

I3C0_SDA

GPIO1_6

H_I3C0_SDA

I/O

CP Board Audio De-serializer UB926_GPIO3

Summary of Contents for J721EXSOMXEVM

Page 1: ...Setup Configuration 13 3 1 Power Requirements 13 3 2 Power ON Switch and Power LEDs 14 3 3 EVM Reset Interrupt Push Buttons 18 3 4 EVM DIP Switches 19 3 5 EVM UART COM Port Mapping 23 3 6 JTAG Emulation 24 4 J721E EVM Hardware Architecture 27 4 1 J721E EVM Hardware Top level Diagram 27 4 2 J721E EVM Interface Mapping 29 4 3 I2C Address Mapping 30 4 4 GPIO Mapping 31 4 5 Power Supply 32 4 6 Reset 3...

Page 2: ...d Port Ethernet Expansion Functional Block diagram 28 18 J721E SOM Power Distribution Block Diagram 32 19 Power ON Sequencing 33 20 Voltage Supervisor Circuit 34 21 LPDDR4 IO Voltage Selection Circuit 35 22 EVM Reset Architecture 39 23 EVM Clock Architecture 40 24 J721E SoC Primary Clock 41 25 J721E SoM LPDDR4 43 26 J721E SoM OSPI and Hyper Flash 44 27 UFS Memory Block Diagram 45 28 eMMC Memory Bl...

Page 3: ...ts 17 6 EVM Push Buttons 18 7 EVM Configuration Switch Function 20 8 EVM Configuration Switch Function 21 9 Wakup Boot Mode Switch SW9 22 10 Main Boot Mode Switch SW8 22 11 UART Port Mapping 23 12 JTAG 1 2 Mux selection 24 13 TI 60 pin Connector J16 Pinout 25 14 cTI20 Pin Connector J1 Refer PROC081E2 SCH Pinout 26 15 TI14 Pin Connector J2 Refer PROC081E2 SCH Pinout 26 16 J721E EVM Interface Mappin...

Page 4: ... 39 MCU I3C Header J33 Pinout 71 40 MAIN I3C Header J32 Pinout 71 41 ADC Header J23 Pinout 72 42 APPLE AUTH Header J9 Pinout 73 43 APPLE AUTH Footprint U108 Pinout 74 44 EVM Expansion Connector J46 Pinout 75 45 EVM Expansion Connector J51 Pinout 77 46 ENET Expansion Board Power Test Points 78 47 ENET Expansion Connector J10 Pinout 80 48 CSI Expansion Connector J52 Pinout 83 49 CSI Expansion Connec...

Page 5: ... customers to evaluate the Processor s performance with flexibility To have flexibility while developing the system different interface expansion boards have been designed Some examples include Infotainment Expansion Board Gateway Ethernet Switch Industrial GESI Expansion Board Fusion CSI2 Expansion Board s 1 1 Key Features The J721E EVM is a high performance standalone development platform that e...

Page 6: ...nk Radio Tuner Interface 2x PCIe Card Slot 1x PCIe M 2 Slot M Key all Gen3 5x Gbit Ethernet 1x RGMII DP83867 1x QSGMII VSC8514 6x Universal Asynchronous Receiver Transmitter UART terminals via 2x USB FTDI UART over USB 2x I3C headers 1x ADC Header Expansion Connectors to support application specific add on boards MLB MLBP Expansion Interface Image Video Capture Expansion Interface Apple Authentica...

Page 7: ...des component s containing at least one Substance of Very High Concern SVHC above 0 1 These uses from Texas Instruments do not exceed 1 ton per year The SVHC s are listed in Table 1 Table 1 REACH Compliance Component Manufacturer Component type Component Part Number SVHC Substance SVHC CAS when available Tensility Power Cable 10 02937 Lead 7439 92 1 Rosenberger FPD Link Connector D4S20G 400A5 C Le...

Page 8: ...ard1 J721E EVM Overview www ti com 8 SPRUIS4A December 2019 Revised May 2020 Submit Documentation Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM Figure 3 shows the overall architecture of the J721E EVM 1 Only one board can be connected to Expansion connector at a time 2 Only one board can be connected to CSI2 Expansion connector at a ...

Page 9: ...r 2019 Revised May 2020 Submit Documentation Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 2 1 J721E EVM Board Identification Figure 4 J721E EVM Board Identification SOM CPB QP Ethernet ...

Page 10: ...SI0 DP0 Hyper Flash Hyper RAM OSPI FLASH J721E EVM Overview www ti com 10 SPRUIS4A December 2019 Revised May 2020 Submit Documentation Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 2 2 J721E SOM Component Identification Figure 5 J721E SOM Component Identification ...

Page 11: ...EXP Mating Conn USB HUB EVM CONFIG SW UFS Memory APPLE AUTH HDR EXT Power Measurement HDR FAN HDR RESET PB MLB MLBP Header MCAN Headers FT2232 UART USB FT4232 UART USB SYS MCU BOOT Switches FPD Link Tuner Deserializer PCIe M 2 Socket 2280 Micro SD Card RGMII PHY Expansion Connectors Battery Holder FPD Link DSI Serializer DSI FPC Connector CS12 Expansion Test Automation Codec Audio Port MCU RGMII S...

Page 12: ... is used with different SOM boards featuring different Jacinto7 processors with different feature sets some of the board s peripherals interfaces may not be supported For the J721E SOM the following interfaces are not supported USB 3 0 uAB USB Type C and 2x USB Type A interfaces are supported 2nd DisplayPort interface single DisplayPort interface is supported These interfaces are identified with a...

Page 13: ... An external power supply is required to power the EVM but is not included as part of the EVM kit The external power supply requirements are Power Jack 2 5 mm ID 5 5 mm OD Nom Voltage 12 VDC Recommended Minimum Current 5000 mA Table 2 Recommended External Power Supply DigiKey Part No Manufacturer Manufacturer Part No SDI65 12 U P6 ND CUI Inc SDI65 12 U P6 SDI65 12 UD P6 ND CUI Inc SDI65 12 UD P6 E...

Page 14: ...Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 3 2 Power ON Switch and Power LEDs The power to the EVM is controlled by the power ON OFF switch SW2 on the CPB To turn the board ON slide the switch in the direction as shown in Figure 9 Figure 9 Power ON OFF Switch ...

Page 15: ...ection Circuit The voltage protection circuit on the EVM protects the board from overvoltage under voltage and transient voltage input cases The safe operation input voltage range is 6 V to 28 V A fault indication and power good LEDs are provided to indicate the power status Table 3 Power LED Status LED ON Status OFF Status LD2 Board Power on Board Power off LD3 Input voltage is 28 V or 6 V Input ...

Page 16: ...to 5 V 3 3 V These 3 3 V and 5 V is the primary voltages for the SoM power management resources Buck Boost controller LM5175 and another Buck controller LM5141 provides 12 V and 3 3 V supplies to the expansion connectors The power good signals of these power regulators are used to generate the SoC PORz Multiple power indication LEDs are provided on board to give users positive confirmation of the ...

Page 17: ...re mentioned in Table 5 Location for each can be identified by searching the assembly drawing for the test point reference number Table 5 Power Test Points Power Supply Test Point Nominal Voltage VINPUT TP20 12 0V VSYS_3V3 TP130 3 3V VCC_12V0 TP39 12 0V VSYS_5V0 TP26 5 0V EXP_3V3 TP43 3 3V VDD_2V5 TP63 2 5V VDD_1V0 TP59 1 0V VCC_1V1 TP60 1 1V VSYS_MCU_5V0 TP117 5 0V VDD_SD_DV TP44 3 3V VSYS_MCUIO_...

Page 18: ...viding Reset inputs and User Interrupts to the processor Table 6 lists the Push buttons that are placed on the Top side of the Common Processor Board Table 6 EVM Push Buttons Sl No Push Buttons Signal Function 1 SW7 MCU_PORz MCU domain Power on Reset input 2 SW5 MCU_RESETz MCU domain Warm Reset input 3 SW4 PORz Main domain Power on Reset input 4 SW6 RESET_REQz Main domain Warm Reset input 5 SW10 S...

Page 19: ...iguration and SoC Boot mode set function 3 4 1 EVM Configuration DIP Switch Figure 13 shows that the common processor board has a dedicated EVM configuration switch SW3 to set the various functions of EVM peripherals Some of the configuration is for peripherals on the CPB while others switches are used to configure peripherals on Expansion Boards For those settings the device specific Expansion Bo...

Page 20: ...e for USB Type C interface USB0 00 OFF OFF DFP Downstream Facing Port SW3 4 OFF USBC_MODE_SEL0 01 OFF ON DRP Dual Role Port 1X ON Don t Care UFP Upstream Facing Port SW3 5 OFF PCIe_1L_MODE_SEL PCIe 1 Lane Interface Mode Select supports port PCIe0 0 OFF Root Complex 1 ON End Point SW3 6 OFF PCIe_2L_MODE_SEL PCIe 2 Lane Mode Select supports port PCIe1 0 OFF Root Complex 1 ON End Point SW3 7 ON CSI_V...

Page 21: ...SOC_I2Cn MUX to select I2C Interface for PMICs 0 OFF PMIC I2C to SoC WKUP interface 1 ON PMIC I2C to External Header test mode only SW2 1 OFF SEL_GPIO8_ALT Selection for PMIC Watchdog Timer GPIO8 0 OFF PMIC watchdog timer control is set with SW2 2 1 ON PMIC I O used for GPIO8 test point SW2 2 ON LEOA_WDOG_DIS Enable Disable selection for PMIC Watchdog Timer 0 OFF PMIC watchdog timer is enabled 1 O...

Page 22: ...ND ADDR 26 27 VCCP RESET 28 SCL 29 SDA 30 31 VCC INT 32 P10 9 P11 10 P12 11 P13 12 P14 13 P15 14 P16 15 P17 16 EP 33 1 4 R359 R768 10K U149 SN74AVC8T245RHL 1 VCCA DIR 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 OE 22 23 VCCB1 24 VCCB2 B1 21 B2 20 B3 19 B4 18 B5 17 B6 16 B7 15 B8 14 11 GND1 12 GND2 13 GND3 EP 25 1 4 R3 R777 10K Tp136 1 4 R358 R322 1K 1 R320 1K 1 R325 1K 1 R914 10K R357 1 4 R326 1K 1...

Page 23: ...w control MCU and WKUP UART ports of the SoC are interfaced with FT2232H for UART to USB functionality and terminated on a micro B connector J43 provided on the CPB When the EVM is connected to a Host using the provided USB cable the computer can establish a Virtual Com Port that can be used with any terminal emulation application The FT2232H is bus powered Virtual Com Port drivers for the FT4232H...

Page 24: ...tion Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 3 6 JTAG Emulation The Common processor board includes XDS110 class on board emulation through the micro B connector J3 It also has an option to support external emulation through MIPI 60 pin header J16 When an external emulator is connected XDS110 emulation circuitry path will be di...

Page 25: ...et the state using the DIP switch SW3 Position 2 which allows GPMC to expansion interface to be selected by default for boot support Table 13 TI 60 pin Connector J16 Pinout Pin No Signal Pin No Signal 1 VSYS_IO_3V3 31 TRC_DATA6 2 MIPI_TMS 32 NC 3 MIPI_TCK 33 TRC_DATA7 4 MIPI_TDO 34 NC 5 MIPI_TDI 35 TRC_DATA8 6 MIPI_TGTRST 36 NC 7 MIPI_RTCK 37 TRC_DATA9 8 MIPI_TRST_PD EXT_MIPI_TRST 38 EXT_MIPI_EMU0...

Page 26: ...pin and the CTI 20 pin JTAG converters Table 14 cTI20 Pin Connector J1 Refer PROC081E2 SCH Pinout Pin No Signal Pin No Signal 1 MIPI_20_TMS 11 MIPI_20_TCK 2 MIPI_20_TRST 12 DGND 3 MIPI_20_TDI 13 MIPI_20_EMU0 4 MIPI_20_TDIS 14 MIPI_20_EMU1 5 MIPI_20_VTREF 15 SYSRST 6 NC key 16 DGND 7 MIPI_20_TDO 17 NC 8 20PJTAG_DET 18 NC 9 MIPI_20_RTCK 19 NC 10 DGND 20 DGND Table 15 TI14 Pin Connector J2 Refer PROC...

Page 27: ...0 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 4 J721E EVM Hardware Architecture This section explains the Hardware Architecture of J721E EVM in detail 4 1 J721E EVM Hardware Top level Diagram Figure 16 shows the functional block diagram of the J721E EVM Figure 16 J721E EVM Functional Block Diagram ...

Page 28: ... V 5 V 3V3 STACKED RJ45 WITH INTEGRATED MAGNETICS X2 LPJG17512AONL Port 1 Port 2 Port 3 Port 4 J721E EVM Hardware Architecture www ti com 28 SPRUIS4A December 2019 Revised May 2020 Submit Documentation Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM Figure 17 shows the Quad Port Ethernet Expansion Board functional block diagram Figure ...

Page 29: ... EEPROM WKUP_I2C0 I2C6 for CSI Expansion CAT24C256WI GT3 CAV24C256WE GT3 for J721E SOM Memory Boot EEPROM MCU_I2C0 AT24CM01 Ethernet RGMII MCU_RGMII1 DP83867ERGZT Ethernet Quad SGMII SERDES0 SGMII2 VSC8514XMK USB 3 1 Type C PD CC Controller SERDES3 USB0 2012670005 PTPS25830QWRHBTQ1 TUSB321RWBR USB 2 0 HUB USB1 TUSB4041IPAPR Display Port SERDES4 DP0 472720001 FPD Link Panel Serializer DSI0 PDS90UB9...

Page 30: ...C Module MCP79410 0x57 6F EVM CPB SoC_I2C0 Apple Authentication Header Footprint 2214BR 10G 0x10 0x11 EVM CPB SoC_I2C0 SERDES REF CLK GEN 2 CDCI6214 0x76 EVM CPB SoC_I2C0 16 bit I2C GPIO Expander 1 TCA6416ARTWR 0x20 EVM CPB SoC_I2C0 24 bit I2C GPIO Expander 2 TCA6424ARGJR 0x21 EVM CPB SoC_I2C0 I2C MUX for both x2LANE and x1LANE PCIe Interface TCA9543APWR 0x70 EVM CPB SoC_I2C0 I2C MUX for M 2 PCIe ...

Page 31: ... MCU_SPI0_ CS0 WKUP_ GPIO0_55 MCU_RGMII1_ INT Input PU Active Low MCU Ethernet Interrupt 0 interrupt pending 1 no interrupt MCU_SPI0_ D0 WKUP_ GPIO0_53 SYS_MCU_ PWRDN Output PD Active low System Power Down 0 normal operation 1 system power down MCU_SPI0_ D1 WKUP_ GPIO0_54 MCU_CAN0_STBz Output PD Active low MCU CAN0 Standby Main Domain EXTINTN GPIO0_0 SOC_EXTINTN Input PU Active low Push button Int...

Page 32: ...shows the SoM s power distribution system The Power to the SoM is derived from the Dual Buck converter 12 V to 5 0 V 3 3 V on the Common Processor Board The J721E processor is powered from a dual TPS6594x PMIC solution which is optimized for the J721E to support a wide variety of use cases Dual load switch TPS22976 Q1 provides the switching option for the LPDDR4 I O power supply 1 1 V 0 6 V Figure...

Page 33: ...5V_CONN1 VBUS_5V_CONN2 V3V3_DP0 V3V3_DP1 VCC_CSI_IO VBUS_USB2 VCC_1V1 VDD_2V5 VDD_1V0 VSYS_MCU_5V0 VCC_12V0_FPD VCC_12V_DSI0 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT EXP_3V3 OUT SOM PMIC R R VSYS_3V3 VSYS_3V3_SOM SYS_MCU_EN VBUS_USBC_CONN OUT LOAD SW TPS22918DBVR VIN ON GPIO_uSD_PWR_EN R VSYS_IO_3V3 VDD_MMC1 OUT LM5140_PG1 LM5140_PG2 LM5141_PG LM5175_PG R R LM5140_PG1 LM5175_PG R LM5141_PG ...

Page 34: ...Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 4 5 2 Voltage Supervisor The power rails are monitored to control the Power ON Reset MCU_PORz for SoC Two supervisor devices are provided to monitor Main power input and VSYS_3V3 Figure 20 Voltage Supervisor Circuit ...

Page 35: ... O supply for the LPDDR4 LPDDR4x Currently the J721E device does not support LPDDR4x This support may be added at a later date The EVM does support this feature if when support is added to the silicon The DIP switch SW1 Bit 1 provides an option to change the logic of D Flip Flop U7 that controls the Load Switches TPS22965TDSGRQ1 and TPS22976NDPUT to decide the I O supply voltages Table 19 DDR I O ...

Page 36: ...gure GPIO4 of LeoA to LP_WKUP1 0x34 7 0 0xC8 GPIO4_CONFIG Read and write to clear the LP_WKUP1 interrupt 0x64 4 0x1 GPIO_INT Set nSLEEP2b and nSLEEP1b to 00 to go to S2R state 0x86 1 0 0x0 NSLEEP2b NSLEEP1b Read and write to clear the ENABLE_INT interrupt 0x65 1 0x1 ENABLE_INT The EVM can be woke from the low power state by pressing the CAN_WAKEn button SW12 4 5 3 2 J721E SoC MCU Only Operation Ta...

Page 37: ...E_RAM_0V85 SOC_I2C2 PM1 0x46 0 01E VDD_CPU_RAM_0V85_REG VDD_CPU_RAM_0V85 SOC_I2C2 PM1 0x47 0 01E VDD_CPU_AVS_REG VDD_CPU_AVS SOC_I2C2 PM1 0x48 0 01E V917_SMPS3_1V1 VDDR_BIAS_1V1 SOC_I2C2 PM1 0x49 0 01E VDDR_IO_DV_SRC VDDR_IO_DV SOC_I2C2 PM1 0x4A 0 01E VDD_CORE_0V8_REG VDD_PHYCORE_0V8 SOC_I2C2 PM1 0x4B 0 01E VDA_PLL_1V8_REG VDA_PLL_1V8 SOC_I2C2 PM1 0x4C 0 01E VDD_PHYIO_1V8_REG VDD_PHYIO_1V8 SOC_I2C...

Page 38: ...it to interface the INA devices with external I2C Master Buffer IC SN74CB3Q3125PWR U69 is used to isolate the External I2C connections from the INA devices The control of this buffer is provided from SYS_PWR_PG which is enabled by default on power up External Power Monitor header details Mfr Part 68002 205HL CON HDR 1X5 2 54MM PITCH ST TH Table 23 External Power Monitor Header Pinouts Header J12 P...

Page 39: ...dware Architecture 39 SPRUIS4A December 2019 Revised May 2020 Submit Documentation Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM Figure 22 EVM Reset Architecture ...

Page 40: ... XTAL 25MHz REF XTAL 22 5792MHz GESI INFO EXPANSION RGMII USB HUB TUSB4041 DSI TO FPD BRIDGE 24MHz XTAL R R XTAL R R 25MHz 24MHz 25MHz CSI2 EXPANSION 25MHz CP Board LVL TXLR GESI INFO EXPANSION SPARE 25MHz 100MHz P N SERDES3 RTC Module 32 768KHz XTAL R R From CP board RTC Module J721E EVM Hardware Architecture www ti com 40 SPRUIS4A December 2019 Revised May 2020 Submit Documentation Feedback Copy...

Page 41: ... to the J721E processor to provide the SoC s Primary clocks WKUP_LFOSC 32 KHz WKUP_OSC0 19 2 MHz and OSC1 22 5792 MHz as shown in Figure 24 Figure 24 J721E SoC Primary Clock The WKUP_OSC0 is required by the processor Both WKUP_LFOSC and OSC1 are optional clocks not required for J721E processing The WKUP_LFOSC can be sourced either on the on board crystal or from the PMIC The OSC1 can be sourced fr...

Page 42: ... 100 MHz CLKGEN_PCIE0_2L_REFCLK_P N R168 R177 CDCI1 Y4 100 MHz HCSL Clock to PCIe0 x2 L Socket 100 MHz CLKGEN_SERDES2_REFCLK_P N R158 R157 CDCI2 Y1 100 MHz HCSL Clock to SoC SERDES2 100 MHz CLKGEN_USB_REFCLK_P N R160 R159 CDCI2 Y2 100 MHz HCSL Clock to SoC USB 100 MHz QSGMII_PHY_REFCLK_P N C108 C109 CDCI2 Y3 125 MHz LVDS Clock to Ethernet Expansion board 125 MHz CLKGEN_PCIE2_2L_REFCLK_P N R123 R12...

Page 43: ...ware Architecture 43 SPRUIS4A December 2019 Revised May 2020 Submit Documentation Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 4 8 Memory interfaces 4 8 1 LPDDR4 Interface The J721E SOM has 4GB of LPDDR4 using single 32Gb x 8 bit wide memory devices arranged in an 32 bit wide bus The LPDDR4 interface can operate up to 3733 Mb s spee...

Page 44: ... to OSPI0 interface of J721E processor The OSPI interface supports single and double data rates with memory speed up to 166 MHz SDR and 200 MHz DDR The SOM board also supports an option to include Hyper Flash Hyper RAM Mfr Part S71KS512SC0 which is a 512 Mb flash 64 Mb DRAM 12 bit Active mux TS3DDR3812RUAR is provided to select either OSPI or HBMC interface The selection of OSPI and hyper flash wi...

Page 45: ...ht 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 4 8 3 UFS Interface The Common Processor board has 32GB UFS memory device Mfr Part THGAF8G8T23BAIL connected to UFS0 port of SoC The UFS memory is Gear3 2Lane capable and supports UFS Version 2 1 Figure 27 UFS Memory Block Diagram ...

Page 46: ...h and MMC1 is interfaced with Micro SD Socket on the Common processor board 4 8 4 1 MMC0 eMMC Interface A 16GB V5 1 compliant eMMC flash memory Mfr Part MTFC16GAPALBH AAT ES is interfaced to MMC0 port of the J721E SoC The flash is connected to 8 bits of the MMC0 interface supporting HS400 double data rates up to 200 MHz External pull up resistors 49 9K are provided on DATA 7 0 CMD and Reset signal...

Page 47: ...ts UHS1 operation including I O operations at both 1 8 V and 3 3 V The Micro SD card interface is set to operate in SD mode by default The I O voltage is controlled using the LDO that provides the I O voltage for the MMC1 port The SD Card power is provided using a load switch which is controlled by a GPIO from I O expander Control signal GPIO_uSD_PWR_EN is driven by the I2C I O expander U31 Port02...

Page 48: ...orage Table 26 Board ID Memory Header Information Header Field Name Size bytes Comments EE3355AA MAGIC 4 Magic Number TYPE 1 Fixed length and variable position board ID header 2 Size of payload BRD_INFO TYPE 1 Payload type Length 2 Offset to next header Board_Name 16 Name of the board Design_Rev 2 Revision number of the design PROC_Nbr 4 PROC number Variant 2 Design variant number PCB_Rev 2 Revisi...

Page 49: ...DP83867ERGZT Gigabit Ethernet PHY and the MCU domain network subsystem NSS of the Processor RJ45 connector J35 with Integrated magnetics LPJG163144NL is used A reference clock of 25 Mhz will be generated onboard using a crystal to DP83867ERGZT Figure 30 MCU Gigabit Ethernet Block The I O supply to the Ethernet PHY is set through selection Resistors R445 and R446 to support both 1 8 V and 3 3 V I O...

Page 50: ... of four modes by using the pull up and pull down options provided The EVM uses the 48 pin QFN package designated with the RGZ suffix which supports only RGMII interface The DP83867 PHY uses four level configurations based on resistor strapping that generate four distinct voltages ranges The resistors are connected to the RX data and control pins that are normally driven by the PHY and are inputs ...

Page 51: ...ved from the physical address of the port 0 to 3 and the setting of the PHY address reversal bit in register 20E1 bit 9 Reference clock to the PHY is generated from SERDES clock generator CDCI2 on the CP board by default Optionally clock generator on the Quad Port Ethernet board also can provide the clock to the PHY with resistor option Table 27 Clock Source Selection Clock Source Install Remove F...

Page 52: ... Hardware Architecture www ti com 52 SPRUIS4A December 2019 Revised May 2020 Submit Documentation Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM Figure 32 Quad SGMII Board I2C Coupling capacitors 0 1 µF added in series at the respective driver ends on the QSGMII data signals The address and clock configurations are shown below PHY0 10...

Page 53: ...n4 operation The EVM also supports the PCIe M 2 socket to interface the M keyed PCIe M 2 form factor modules which are not included in the EVM kit 4 11 1 X1 Lane PCIe Interface The x1 lane PCIe interface includes one x4 lane PCIe connector of part number Amphenol 10142333 10111MLF which supports PCIe Gen4 operation The pin out of the connector follows PCIe standard The SERDES0 port of J7 SoC is co...

Page 54: ...CL I2CADD 0x70 J721E EVM Hardware Architecture www ti com 54 SPRUIS4A December 2019 Revised May 2020 Submit Documentation Feedback Copyright 2019 2020 Texas Instruments Incorporated Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM Figure 34 PCIe Interface for SERDES0 Figure 35 PCIe SMBUS Block Diagram ...

Page 55: ...cards and SoC Resistor options are provided to select the clock source for host and end point operation For PCIe host operation The add on cards can have clocks driven by SOC or clock generator Selection can be made through resistors as shown in Table 28 Table 28 Reference Clock Selection for PCIe Host Operation Clock Selected Mount Unmount Reference Clock for SOC from clock generator R194 R195 C9...

Page 56: ... device mode For choosing Host or device operation of PCIe card following resistors must be mounted unmounted as mentioned in Table 30 Table 30 Resistors for Selecting PCIe Card Host or Device Operation Mode Mount Demount Host mode R674 R675 R679 Device mode R675 R674 R679 Additional Options Optional MDIO bus and USB2 0 interface is supported for external PCIe add on cards SoC Main domain CPSW9G0 ...

Page 57: ...ces are pinmuxed with this SERDES1 port Figure 38 PCIe Interface for SERDES1 I2C0 from SoC is used for control purposes and is connected to SMBUS on the connector through I2C switch The link activation signal INT from both the X1 and X2 lane PCIe connectors is terminated to I2C switch Reset A dip Switch SW3 is provided to select the reset source for host and end point PCIe operation In case of hos...

Page 58: ...tor R54 R211 C44 R56 R210 C51 For PCIe Endpoint operation The SoC can have the clock driven by add on cards or clock generator Selection can be made through resistors as shown in Table 32 Table 32 Reference Clock Selection for PCIe Endpoint Operation Clock Selected Mount Unmount Reference clock for SOC from clock generator R214 R211 C44 R213 R210 C51 Reference clock for SOC from PCIe connector R21...

Page 59: ...l be used to change the I O level of SMBUS signals to 1 8 V The link activation signal WKUP from PCIe connector is terminated to the test point TP85 Reset Reset signal to the SSD add on module is controlled by GPIO expander The GPIO signal is pulled low with a resistor 10K by default to ensure PCIe Reset PERST remains asserted until SoC releases reset Clock A clock generator CDCI 2 is provided to ...

Page 60: ...ort UFP modes In CP board DRP DFP and UFP modes can be selected through an EVM Configuration dip switch SW3 The Dip switch settings are given in Table 6Table 6 Figure 41 USB3 1 Type C Interface The AC coupling capacitors are provided on TX lines of Super speed signals and common mode filters MCZ1210DH900L2TA0G are used at all the differential pairs ESD protection diodes are provided on all require...

Page 61: ...signals are connected to upstream port of USB 2 0 Hub TUSB4041IPAPR The four downstream ports from USB Hub are connected are shown below 2 USB ports are terminated to Type A Stacked Connector AU Y1008 2 1 USB port is connected to 4 Pin Header PCIe Card WiFi BT 1 USB port is connected to EVM Expansion connector The reference clock to the USB HUB is provided using 24 MHz crystal and also an optional...

Page 62: ...n optional interface provided for a future version of the J7 SoC only it is not supported in the J721E EVM 4 13 CAN Interface The four CAN ports of J721E SoC MCU_MCAN0 MCU_MCAN1 MCAN0 and MCAN2 is supported on the Common Processor board as explained below MCU CAN0 The MCU CAN0 port of J721E SoC is connected to the CAN transceiver with Wake function supported device TCAN1043 Q1 A 2 pin header J29 6...

Page 63: ...al held high with external pull up by default The GPIO control from MCU domain provided to pull the line low MAIN CAN0 Supports WAKE function The MAIN CAN0 port of J721E SoC is connected to the CAN transceiver with Wake function supported device TCAN1043 Q1 A 2 pin header J24 68002 202HLF is provided inline for user probe option The output of the CAN transceiver is terminated to a 4 pin header J27...

Page 64: ...The MAIN CAN2 port of J721E SoC is connected to the CAN transceiver Mfr Part TCAN1042HGVD A 2 pin header J25 68002 202HLF is provided inline for user probe option This port does not support WAKE function The signals MCAN2_H and MCAN2_L are terminated to a 3 pin header J28 68001 403HLF with 120E split termination The STB signal is an active High signal held high with external pull up by default The...

Page 65: ...r recover the audio signals from Tuner interface using HSD connector Mfr Part D4S20G 400A5 C The de serializer will recover up to eight digital audio channels plus I2C channel across digital link This audio signal shall be connected to McASP11 port of J721E SoC through 1 3 DEMUX SN74CBT16214CDGGR The channel selection is supported by both GPIO expander and EVM configuration DIP switch SW3 The I2C3...

Page 66: ...ridge and FPD Link III signals are terminated to HSD connector of Mfr Part D4S20G 400A5 C to interface with display panel Reference clock to the FPD bridge is provided from Peripheral clock generator CDCEL and onboard clock oscillator ASDMB 25 000MHZ XY T with the resistor option The default clock source is selected to onboard clock oscillator The I2C1 signals of J721E being used for controlling o...

Page 67: ...ndary output clock from the fan out buffer is routed to EVM expansion connector to interface to Infotainment Audio Codec devices The MODE pin is held LOW to select I2C as control interface Codec is configured over I2C3 interface Default I2C address is set to 0x44 The device reset is controlled by the I2C GPIO expander using a I2C3 master port Line IN Port Single ended Stereo 1x Line Input signal f...

Page 68: ...7 J721E DRA829 TDA4VM Evaluation Module EVM Head Phone Port 6x differential digital Outputs from the CODEC is converted to single ended and terminated to stereo Audio Jack J40 top port and stacked audio jack J41 with head phone circuit Port Mapping Common Processor board audio ports are mapped as below 3x Standard 3 5mm stacked Stereo Audio Jack Mfr Part STX 4235 3 3 N is provided for 2x MIC IN 1x...

Page 69: ...J721E SoC 4K UHD Display 3840 x 2160 120 Hz MST Multi stream support up to Two 4K UHD Displays 3840 x 2160 60 Hz MST can be supported by CP board display port interface Standard full size Molex display connector Mfr Part 472720001 is used to interface with displays Figure 53 Display Port Block Diagram Separate ESD protection devices of Mfr Part TPD1E05U06DPY are used for main and auxiliary data ch...

Page 70: ...der J22 QSH 020 01 L D DP A Table 38 MLB Header Pinout Pin No Signal Pin No Signal 1 MLB0_MLBSIG_N 2 H_MLB0_MLBCLK 3 MLB0_MLBSIG_P 4 NC 5 NC 6 H_MLB0_MLBSIG 7 NC 8 NC 9 MLB0_MLBDAT_N 10 H_MLB0_MLBDAT 11 MLB0_MLBDAT_P 12 NC 13 NC 14 NC 15 NC 16 H_MLB0_REFCLK 17 MLB0_MLBCLK_N 18 NC 19 MLB0_MLBCLK_P 20 NC 21 DGND 22 DGND 23 NC 24 MLB0_GPIO0 25 MLB_RSTz 26 NC 27 NC 28 NC 29 NC 30 NC 31 NC 32 NC 33 I2C...

Page 71: ... Processor board The signal path is disconnected by default using resistors R192 and R193 The mux selection is controlled by I2C GPIO Expander2 I2C ADD 0x22 I2C0 Port16 Table 39 and Table 40 lists the I3C Header pinouts Table 39 MCU I3C Header J33 Pinout Pin No Signal 1 DGND 2 MCU_I3C0_SDA 3 MCU_I3C0_SCL Table 40 MAIN I3C Header J32 Pinout Pin No Signal 1 DGND 2 MCU_I3C0_SDA 3 MCU_I3C0_SCL 4 21 AD...

Page 72: ..._AIN6 7 DGND 8 DGND 9 MCU_ADC0_AIN4 10 MCU_ADC0_REF_P 11 MCU_ADC0_AIN2 12 MCU_ADC0_REF_N 13 DGND 14 DGND 15 MCU_ADC0_AIN5 16 MCU_ADC_EXT_TRIGGER0 17 NC 18 NC 19 DGND 20 DGND 4 22 RTC Interface A real time clock module Mfr Part MCP79410 I SN is connected I2C0 interface of J721E SoC RTC device is being powered by 3 3 V and a battery holder BC501SM is connected to VBAT pin for external battery power ...

Page 73: ...e authentication board can be interfaced with J721E SoC in two options one is module interface and the other is device interface Figure 57 Apple Authentication Block Diagram Module Interface Common Processor board have a 2 54 mm Dual row 10 Pin Receptacle Mfr Part 2214BR 10G I2C0 Port of J721E SoC and Reset from GPIO Expander is terminated to this connector 3 3 V supply is provided to the connecto...

Page 74: ...hown in Table 43 Table 43 APPLE AUTH Footprint U108 Pinout Pin No Signal Description 6 I2C0_SCL I2C slave interface clock connection 2 I2C0_SDA I2C slave interface data connection 7 APPLE_AUTH_RSTz Reset Active low 8 VSYS_IO_3V3 Power 3 3 V 1 9 DGND Ground 3 4 5 NC Not Connected 4 24 EVM Expansion Connectors The Common processor board includes an Expansion connector of QSH 060 01 L D A K with 5mm ...

Page 75: ..._DE SPI6_CLK 35 NC 36 VOUT0_PCLK SPI6_D1 37 DGND 38 DGND 39 VOUT0_DATA0 PRG1_RGMII2_RD0 40 VOUT0_DATA19 PRG1_RGMII1_TD3 41 VOUT0_DATA2 PRG1_RGMII2_RD2 42 VOUT0_DATA16 PRG1_RGMII1_TD0 43 VOUT0_DATA1 PRG1_RGMII2_RD1 44 VOUT0_DATA20 PRG1_RGMII1_TX_CTL 45 VOUT0_DATA3 PRG1_RGMII2_RD3 46 VOUT0_DATA18 PRG1_RGMII1_TD2 47 VOUT0_DATA4 PRG1_RGMII2_RX_CTL 48 VOUT0_DATA21 PRG1_RGMII1_TXC 49 VOUT0_DATA6 PRG1_RG...

Page 76: ...46 Pin No Signal Pin No Signal 91 PRG0_RGMII2_TX_CTL 92 MCASP6_ACLKR PRG1_RGMII1_RX_CTL 93 MCASP2_AXR0 PRG0_RGMII2_TD3 94 MCASP6_AXR0 PRG1_RGMII1_RD2 95 DGND 96 DGND 97 MDIO0_MDC 98 PRG0_MDIO0_MDC I2C5_SDA 99 MDIO0_MDIO 100 PRG0_MDIO0_MDIO I2C5_SCL 101 SPI3_D0 102 MCASP0_AXR13 PRG0_PWM0_B2 103 SPI3_D1 104 NC 105 SPI3_CLK 106 RGMII_REFCLK 107 DGND 108 DGND 109 I2C0_SCL 110 MCASP1_ACLKX 111 I2C0_SDA...

Page 77: ...22 EXP_REFCLK 23 EXP_EEPROM_A2 24 NC 25 BOARDID_EEPROM_WP 26 PRG1_IEP0_EDIO_OUTVALID 27 GPIO0_6 28 PERIPH_RSTz 29 GPIO0_61 30 RESETSTATz 31 UB926_GPIO2 32 EXP_MUX1 33 UB926_GPIO3 34 EXP_MUX2 35 NC 36 EXP_MUX3 37 NC 38 NC 39 DGND 40 DGND 41 GPMC0_A1 42 GPMC0_A22 43 GPMC0_A2 44 GPMC0_DIR 45 GPMC0_A3 46 GPMC0_A17 47 GPMC0_A4 48 GPMC0_BE1 49 GPMC0_A5 50 GPMC0_A16 51 GPMC0_A7 52 GPMC0_A21 53 GPMC0_A6 5...

Page 78: ...d on Top side of the processor board This section provides an overview of the different interfaces and circuits on the Quad port Ethernet Expansion Board 4 25 1 Power requirements The Expansion Card utilizes power from Common processor board through expansion connector and it has two Low Drop Out circuits to supply Quad Port SGMII PHY with the necessary voltage and the power required Test points f...

Page 79: ...pansion Board which can be configured by I2C0 of the J721E SOC The I2C address of this clock generator is 0x77 and this address conflicts with CDCI Chip on Common processor Board An I2C switch on Quad port Ethernet Expansion Board is used to remove the address conflict by either connecting any one of the clock generators Figure 59 CDCI I2C Isolation Circuit Set the CDCI_I2C_SEL I O EXP bit high to...

Page 80: ...ted by an I2C GPIO Expander2 I2C ADD 0x22 I2C0 Port21 in the common processor board Table 47 lists the ENET expansion connector pinouts Table 47 ENET Expansion Connector J10 Pinout ENET Expansion connector Interface J10 Pin No Signal 1 DGND 2 NC 3 NC 4 DGND 5 NC 6 NC 7 DGND 8 NC 9 NC 10 DGND 11 VSYS_IO_3V3 12 VSYS_IO_3V3 13 DGND 14 EEPROM_A0 15 EEPROM_A1 16 EEPROM_A2 17 DGND 18 EEPROM_WP 19 REFCLK...

Page 81: ...B from the SERDES domain of J721E processor are used 4 25 4 1 Quad Port SGMII PHY Default Configuration The J721E EVM uses the 138 pin QFN package designated with the XMK suffix that supports only the SGMII interface The VC8514 device includes three external PHY address pins PHYADD 4 2 to allow control of multiple PHY devices on a system board sharing a common management bus These pins set the mos...

Page 82: ... Camera Serial Interface CSI0 and CSI1 of J721E SoC is interfaced to this CSI expansion connector J52 on the CP board The Common Processor board supports the Auxiliary CSI expansion connector that is reserved for CSI2 port of future J7 SoC Power 12 V and 3 3 V control GPIOs and reference clock to these CSI expansion boards are provided from Common Processor board through CSI expansion connector Op...

Page 83: ...EFCLK_DV 30 EXP_3V3 11 CSI0_RX0_N 31 CSI1_RX0_N 12 DGND 32 EXP_3V3 13 CSI0_RX1_P 33 CSI1_RX1_P 14 CSI2_RSTZ_DV 34 EXP_3V3 15 CSI0_RX1_N 35 CSI1_RX1_N 16 DGND 36 EXP_3V3 17 CSI0_RX2_P 37 CSI1_RX2_P 18 CSI2_A_GPIO2_DV 38 VCC_CSI_IO 19 CSI0_RX2_N 39 CSI1_RX2_N 20 CSI2_A_GPIO3_DV 40 VCC_CSI_IO Table 49 CSI Expansion Connector J48 Pinout CSI2 Connector Interface J48 Pin No Signal Pin No Signal 1 VCC_12...

Page 84: ... 2020 Texas Instruments Incorporated Revision History Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Original December 2019 to A Revision Page Update was made to Figure 3 8 Updates were made in Section 4 26 82 Update was made in Table 49 83 ...

Page 85: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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