Board Layout
13
SBOU205 – March 2018
Copyright © 2018, Texas Instruments Incorporated
INA1620EVM Audio Amplifier Evaluation Module
5
Board Layout
This section provides a description of the INA1620EVM board layout and layer illustrations.
5.1
Layout
The board layout for the INA1620EVM is shown in
and
. The top layer consists of all
signal traces and is poured with a solid ground plane. Traces for both the left and right channel were kept
as balanced as possible to eliminate any impedance mismatch due to trace impedance. Power supply
decoupling capacitors C6 and C8 were placed as close as possible to the supply pins of the INA1620. The
placement of the remaining passive components was kept as close and symmetrical as possible to
minimize loop areas, which can couple noise and interference into the INA1620. This via stitching also
helps shunt ground currents from the top ground pour, which is interrupted by traces and components,
down to the bottom ground pour, which has much less interruption. The bottom layer was used to route
only one signal, the V
cc
connection to the EN pin pullup resistor. Note that due to the size of the copper
pour for the thermal pad on the bottom layer, the thermal performance specified in the INA1620 datasheet
may not be met on the INA1620EVM. Refer to the application report,
for more information.