24-bpc GPU
R0 (LSB)
R1
R2
R3
R4
R5
R6
R7 (MSB)
G0 (LSB)
G1
G2
G3
G4
G5
G6
G7 (MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7 (MSB)
CLKSEL
DUT_GND
SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V
1p2V
3p3V
VCCIO
DUT_GND SIGNAL_GND
VCC
1p8V
2p5V
3p3V
3p3V
P1
P2
P3
P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
U1
PIN 1
JMP7
JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
LVDS
Timing
Controller
(6bpc, 18bpp)
100
Pa
n
e
l C
o
n
n
e
ct
o
r
Ma
in
Bo
a
rd
C
o
n
n
e
ct
o
r
100
100
100
24bpp LCD Display
F
PC
C
a
b
le
To Column Driver
To Row Driver
CLKIN
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
Notes:
Current setup uses rising edge triggered clocking. If rising edge triggered
clocking is desired, place jumper to create LOW level input at JMP7.
Leave output Y3 NC (No Connection).
R0, R1, G0, G1, B0 and B1 are for improved image quality purposes. The
GPU should dither 24-bit output pixel down to 18-bit per pixel.
C1
C3
C4
C5
C10
C9
C8
C7
C6
C11
C12
C13
C14
C15
C2
R2
R1
PCB Construction
10
SNLU233 – October 2017
Copyright © 2017, Texas Instruments Incorporated
LVDS83BTSSOPEVM User’s Guide
Figure 9. 24-Bit Color Host to 18-Bit LCD Panel Application
3
PCB Construction
This section discusses the construction of the LVDS83BTSSOPEVM boards. The section includes the
board layers to show how the board was built.
3.1
LVDS83BTSSOPEVM Board Layout
This EVM was designed to show the implementation of the SN75LVDS83B device on a 6-layer board.
The pin assignments of the input ports of the SN75LVDS83B device are optimized for the PCB mount of
the GPU connector. This allows easy routing of the traces and a minimal number of vias to preserve good
signal integrity. Every effort was made to keep the routing as clean as possible to the GPU connectors.
The board was designed to maintain 50
Ω
to GND single-ended impedance for each individual trace. This
design uses FR4 – TurboClad 370 material with the board stack up shown in
, and requires the
traces to be 9.25 mil wide and 5 mils above the GND reference plane. A minimum spacing of 3 times the
trace width was maintained to all other components to prevent unwanted coupling.
A differential routing scheme that creates 100-
Ω
impedance between the differential traces could have
also been implemented equally as well with this device.
