Gigabit Ethernet PHY
KSZ9031RNX
K2G SoC
RJ45
Connector with
Magnetics
LPJG16314A4NL
RGMII_TXCLK
RGMII_TXCTL
RGMII_TXD [0-3]
RGMII_RXCLK
RGMII_RXCTL
RGMII_RXD [0-3]
MDIO_CLK
MDIO_DATA
TXC
TX_CTL
TD [0-3]
RXC
MDIO
RX_CTL/PHYAD2
RD [0-3] / MODE [0:3]
MDC
TXRXPA
TXRXMA
TXRXPB
TXRXMB
TXRXPC
TXRXMC
TXRXPD
TXRXMD
Copyright © 2016, Texas Instruments Incorporated
System Description
30
SPRUI65A – April 2016 – Revised January 2018
Copyright © 2016–2018, Texas Instruments Incorporated
K2G General Purpose Evaluation Module (EVMK2G)
3.14 Gigabit Ethernet
The Gigabit Ethernet PHY (KSZ9031RNX) from MICREL is interfaced to the RGMII port of the processor
as shown in
The RJ45 connector with magnetics is interfaced to the MDI (media dependent interface) port of PHY. The
PHY address, PHYAD [2:0], is sampled and latched at power-up/reset and is configurable to any value
from 0 to 7. Each PHY address bit is configured as:
•
Pull-up = 1
•
Pull-down = 0
The MODE [3:0] pins are sampled and latched at power-up/reset. Each Mode bit is configured as:
•
Pull-up = 1
•
Pull-down = 0
The MODE pins are set for RGMII mode (10/100/1000 speed half/full-duplex).
Reference clock for PHY is provided by the 25-MHz crystal, Y9. (See
)
Figure 19. Gigabit Ethernet Interface Block Diagram