Texas Instruments EVMK2G, User Manual, Page: 26 / 83

K2G SoC
SPI FLASH
N25Q128A13ESF40F
RESET#
BMC
AND GATE
SOC_RESETSTATz
FLASH_WP#
FLASH_RESET#
3.3 V
GPIO
SPI1_MOSI
SPI1_CSn0
SPI1_MISO
SPI1_CLK
Q
#S
D
#HOLD
C
#W
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System Description
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26 SPRUI65A – April 2016 – Revised January 2018
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K2G General Purpose Evaluation Module (EVMK2G)
3.9 SPI Flash
The SPI Flash (N25Q128A13ESFESF40F) from Micron is a 128-Mbit Serial Flash interfaced as shown in
Figure 13 . The Serial Flash is interfaced to the SPI1 port of the processor and is connected to chip
select 0.
The write protection for the Flash is controlled by the BMC. The Hold signal (to pause the serial
communication without deselecting the device) is connected to SoC GPIO with a default pull-up.
Figure 13. SPI Flash Block Diagram