2.5 ASRAM/NOR Flash Interface
SPRUGZ3A—May 2011
KeyStone Architecture External Memory Interface (EMIF16) User Guide
2-7
Chapter 2—Architecture
www.ti.com
2.5.4 Switching Waveforms
This section describes the read and write asynchronous cycles and associated switching
waveforms for different operating modes.
2.5.4.1 Asynchronous Reads
An asynchronous read cycle proceeds as follows (see
1 and 2 below):
•
At the start of the setup period:
–
Setup, strobe, and hold values are set according to the R_SETUP,
R_STROBE, and R_HOLD values programmed in the Async 1/2/3/4 Config
Register
–
EMIFCE becomes active (LOW) if not already active from previous
asynchronous access
–
EMIFBE1/EMIFBE0 become active (LOW)
–
Address on address lines EMIFA[23:0] become valid
•
At the start of the strobe period, EMIFOE becomes active (LOW).
•
At the start of the hold period:
–
EMIFOE becomes inactive (HIGH)
–
Data is sampled on clock rising edge concurrent with the beginning of the
hold period (and end of strobe)
•
At the end of the hold period:
–
EMIFCE goes inactive (HIGH) only if no read/write access to the chip select
space is still pending.
–
EMIFBE[1:0] become inactive.
–
Address on address lines EMIFA[23:0] become invalid.
Note—
1: In case an asynchronous request cannot be serviced in a single
asynchronous access cycle, multiple cycles will be needed to complete the
single read or write request. In this case, the EMIF16 enters the setup phase
directly without incurring turnaround cycles.
Note—
2: If the entire read or write access has completed and there are more
requests pending, the EMIF16 enters turnaround state and waits for
programmed turnaround cycles.
L
H
H
L
H
High-Z
Output disabled
L
H
H
H
L
High-Z
Output disabled
L
L
X
L
L
Data Out on EMIFD[15:0]
Write
L
L
X
H
L
Data Out on EMIFD[7:0]
High-Z EMIFD[15:8]
Write
L
L
X
L
H
Data Out on EMIFD[15:8]
High-Z on EMIFD[7:0]
Write
End of Table 2-3
Table 2-3
Control Signal Truth Table (Part 2 of 2)
EMIFCE
EMIFWE
EMIFOE
EMIFBE[1]
EMIFBE[0]
I/O
Operating Mode
