2.5 ASRAM/NOR Flash Interface
2-6
KeyStone Architecture External Memory Interface (EMIF16) User Guide
SPRUGZ3A—May 2011
Chapter 2—Architecture
www.ti.com
For writes, EMIFCE, EMIFWE, EMIFBE[1:0] must be active in order to initiate a write
cycle. Active status of these control signals for write is defined as EMIFCE = LOW,
EMIFWE = LOW and EMIFBE1 = LOW and/or EMIFBE0 = LOW. If any one of these
goes inactive, the write cycle will be terminated.
For reads, EMIFCE = LOW, EMIFWE = HIGH, EMIFOE = LOW, EMIFBE1 = LOW
and/or EMIFBE0 = LOW in order to successfully initiate a read cycle. Any of these
signals going inactive will terminate the read cycle.
The data input setup and hold timing must be referenced to the edge of the signal that
initiates or terminates a read or write. The truth table in
shows various
control signals and the resulting operating mode.
2.5.2 Programmable EMIF16 Parameters
EMIF16 module allows the user to program various parameters for all four chip selects:
•
Setup
- Time between the beginning of a memory cycle (chip select low, address
valid) and the activation of read or write strobe. Minimum value is 1 (0 treated
as 1).
•
Strobe
- Time between the activation and deactivation of the read (EMIFOE) or
write (EMIFWE) strobe. Minimum value is 1 (0 treated as 1).
•
Hold
- Time between the deactivation of the read or write strobe and the end of
the cycle (which may be either an address change or the deactivation of the chip
select signal. Minimum value is 1 (0 treated as 1).
•
Turnaround
- Cycles between the end of one asynchronous memory access and
the start of another asynchronous memory access minus one cycle. This delay is
not incurred between a read followed by read or a write followed by a write to
same chip select.
•
Data width
- Width of the asynchronous device’s data bus (8/16-bit).
The setup, strobe and hold parameters are in terms of EMIF16 clock cycles. Note that
EMIF16 is clocked at CPU/6 (166.67 MHz for 1 GHz CPU frequency). The setup,
strobe and hold values for reads can be calculated as follows (assume CPU=1 GHz).
Determine the read cycle time from device datasheet (tRC). Now tRC = r
r_ r_hold. For example, if tRC = 86ns, 86 = r r_ r_hold. Since
each of the 3 parameters are in terms of CPU/6, (86/6) = r r_ r_hold.
This should be rounded off to the next higher integer, in this case 15. Determine from
the memory device datasheet timing diagrams what each of the 3 parameters should be.
After rounding off, always add the extra memory cycle(s) to the strobe. Similarly,
w_setup, w_strobe and w_hold can be determined.
2.5.3 EMIF16 Truth Table
Table 2-3
Control Signal Truth Table (Part 1 of 2)
EMIFCE
EMIFWE
EMIFOE
EMIFBE[1]
EMIFBE[0]
I/O
Operating Mode
H
X
X
X
X
High-Z
Deselect/Power Down
X
X
X
H
H
High-Z
Deselect/Power Down
L
H
L
L
L
Data In on EMIFD[15:0]
Read
L
H
L
H
L
Data In on EMIFD[7:0]
Read
L
H
L
L
H
Data In on EMIFD[15:8]
Read
L
H
H
L
L
High-Z
Output disabled
