Texas Instruments DS90UB949A-Q1EVM User Manual Download Page 7

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DS90Ux949A

FPD-Link III

Deserializer

Video

Processor

Video Processor Board

Cluster, Head Unit

Dual FPD-LINK III

Display

HDMI

I2C

oLDI

FPD-Link III

2 Lane

VDDIO

1.8 V

IDx

DOUT0+

DOUT0-

1.1 V

IN_CLK-/+

HDMI

DDC

CEC

DOUT1+

DOUT1-

RIN0+

RIN0-

RIN1+

RIN1-

CLK+/-

CLK2+/-

oLDI

D0+/-

D1+/-

D2+/-

D3+/-

D4+/-

D5+/-

D6+/-

D7+/-

DS90Ux949A-Q1

Serializer

DS90Ux948-Q1

Deserializer

IDx

D_GPIO

(SPI)

D_GPIO

(SPI)

LVDS Display

(2880x1080)

or Graphic

Processor

Graphics

Processor

IN_D0-/+

IN_D1-/+

IN_D2-/+

I2C

VDDIO

(3.3 V / 1.8 V)

3.3 V

I2C

1.25 V

1.8 V

HDMI

High Definition Multimedia Interface

HDCP*

High-Bandwidth Content Protection

* Only on DS90UH devices

HPD

www.ti.com

Applications Diagram

SNLU232A – August 2018 – Revised May 2019

Submit Documentation Feedback

DS90UH949A-Q1EVM or DS90UB949A-Q1EVM User's Guide

1.5

Applications Diagram

Figure 1-1

and

Figure 1-2

show the use of the chipset in a display application.

Figure 1-1. Applications Diagram

1.6

Typical Configuration

Figure 1-2. Typical Configuration

Summary of Contents for DS90UB949A-Q1EVM

Page 1: ...DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide Literature Number SNLU232A August 2018 Revised May 2019 ...

Page 2: ...LP Software Setup 14 1 11 1 System Requirements 14 1 11 2 Download Contents 14 1 11 3 Installation of the ALP Software 14 1 11 4 Start Up Software Description 15 1 11 5 Information Tab 17 1 11 6 HDMI Tab 18 1 11 7 Pattern Generator Tab 19 1 11 8 Registers Tab 20 1 11 9 Registers Tab Address 0x00 Selected 21 1 11 10 Registers Tab Address 0x00 Expanded 22 1 11 11 Scripting Tab 23 1 12 Troubleshootin...

Page 3: ...5 1 18 ALP No Devices Error 26 1 19 Windows 7 ALP USB Driver 26 1 20 ALP in Demo Mode 27 1 21 ALP Preferences Menu 27 1 22 Typical Test Setup for Video Application 28 1 23 Typical Test Setup for Evaluation 28 A 1 Schematic Block Diagram 39 A 2 Schematic DS90UH949A Q1 and Power Decoupling 40 A 3 Schematic MSP430 41 A 4 Schematic PDB IDx and MODE_SEL Switches 42 A 5 Schematic HDMI HSD SMA I2C DDC CE...

Page 4: ...k III Output Signals P1 HSD Connector 11 1 5 Alternative SMA FPD Link III Output Signals Note SMAs are Not Connected by Default From the Factory 11 1 6 HDMI Input Signals 11 1 7 USB2ANY Connector 11 1 8 I2C CCI Interface Header J25 11 1 9 GPIO Audio Interface 12 1 10 SPI D_GPIO Interface 12 1 11 MODE_SEL 1 0 Settings 12 1 12 Configuration Select MODE_SEL0 SW DIP8 S2 12 1 13 Configuration Select MO...

Page 5: ...e same differential link In backward compatible mode the device supports up to WXGA and 720p resolutions with 24 bit color depth over a single differential link The device supports up to 7 1 audio channels Audio data received from the HDMI stream is encrypted serialized and sent out on the FPD Link III stream to a compatible deserializer Up to 8 channel I2S interface with maximum bit rate of 192 k...

Page 6: ...l shielded twisted pair STP Q cables Backward compatible to DS90Ux926Q Q1 DS90Ux928 Q1 DS90Ux940 Q1 and DS90Ux948 Q1 FPD Link III deserializers Speed BIST Supports 7 1 multiple I2S 4 data channels Single 12 V power supply for EVM 1 8 V LVCMOS I O interface 1 8 V or 3 3 V compatible LVCMOS I2C interface Automotive grade product AEC Q100 grade 2 qualified 1 3 System Requirements To demonstrate the f...

Page 7: ...ocessor Graphics Processor IN_D0 IN_D1 IN_D2 I2C VDDIO 3 3 V 1 8 V 3 3 V I2C 1 25 V 1 8 V HDMI High Definition Multimedia Interface HDCP High Bandwidth Content Protection Only on DS90UH devices HPD www ti com Applications Diagram 7 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide...

Page 8: ... factory setting S3 IDx 0x18 S3 switch position 1 ON all other switch positions OFF default factory setting S6 MODE_SEL1 S6 switch position 1 ON all other switch positions OFF default factory setting 2 Connect P1 DOUT 1 0 to the compatible deserializer for example the DS90Ux940 Q1EVM or DS90Ux948 Q1EVM using a STP cable default 3 Connect J8 to 12 V a Optional power options available see Table 1 3 ...

Page 9: ...8 7 6 5 4 3 2 1 DS90Ux949A VDD_I2C SCL SDA GND VDD_DDC DDC_SCL DDC_SDA GND 2 3 4 5 Connect to PC for I2C register access I2C Default Configuration www ti com Quick Start Guide 9 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide Figure 1 3 Interfacing to the EVM ...

Page 10: ... Jumper Settings J5 Connect 2 and 3 J9 Connect 2 and 3 J11 Connect 2 and 3 J12 Connect 2 and 3 J20 Connect 2 and 3 J23 Connect 2 and 3 J40 Connect 2 and 3 J41 Connect 2 and 3 1 9 Default Switch Settings Ensure that the board has the default board switch settings Table 1 2 Default Board Switch Settings Switch Switch Settings S2 1 ON silk screen L side 2 8 OFF silk screen H side S3 1 ON silk screen ...

Page 11: ...rnative to Main Power If used remove R13 Table 1 4 FPD Link III Output Signals P1 HSD Connector Designator Port Signal P1 1 FPD Link III Port 0 DOUT0 P1 3 DOUT0 P1 2 FPD Link III Port 1 DOUT1 P1 4 DOUT1 Table 1 5 Alternative SMA FPD Link III Output Signals Note SMAs are Not Connected by Default From the Factory Designator Port Signal J15 FPD Link III Port 0 DOUT0 J17 DOUT0 J14 FPD Link III Port 1 ...

Page 12: ...ink III mode Serial Clock J26 28 D_GPIO1 MISO I O in Dual FPD Link III mode Master In Slave Out J26 26 D_GPIO0 MOSI I O in Dual FPD Link III mode Master Out Slave In Configuration of the device may be done through the MODE_SEL 1 0 These modes are latched into register location during power up Table 1 11 MODE_SEL 1 0 Settings Mode Setting Function EDID_SEL Display ID Select 0 Look for remote EDID i...

Page 13: ...7 1 1 0 8 1 1 1 The strapped values can be viewed and or modified in the following locations EDID_SEL Latched into BRIDGE_CTL 0 EDID_DISABLE 0x4F 0 AUX_I2S Latched into BRIDGE_CFG 1 AUDIO_MODE 1 0x54 1 EXT_CTL Latched into BRIDGE_CFG 7 EXT_CONTROL 0x54 7 COAX Latched into DUAL_CTL1 7 COAX_MODE 0x5B 7 REM_EDID_LOAD Latched into BRIDGE_CFG 5 0x54 5 1 Only set one high Table 1 14 IDx SW DIP8 S3 1 Des...

Page 14: ...xe that was extracted to a temporary location on the local drive of your PC There are 7 installation steps after the setup wizard starts 1 Click the Next button in the ALP Setup Wizard to start the installation 2 Select I accept the agreement and then click the Next button 3 Select the location to install the ALP software and then click the Next button 4 Select the location for the start menu shor...

Page 15: ...og LaunchPAD shortcut from the start menu The default start menu location is under All Programs Texas Instruments Analog LaunchPAD vx x x Analog LaunchPAD to start MainGUI exe Figure 1 4 Launching ALP The application should come up in the state shown in Figure 1 5 If it does not see Section 1 12 Troubleshooting ALP Software NOTE The ALP window graphics in this document show DS90UH949 and the docum...

Page 16: ...orated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide Under the Devices tab select DS90UH949 for the DS90UB949A Q1EVM or DS90UB949 for the DS90UB949A Q1EVM to open up the device profile with its associated tabs Figure 1 5 Initial ALP Screen After selecting the DS90Ux949 the screen shown in Figure 1 6 should appear Figure 1 6 Follow Up Screen ...

Page 17: ... Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide 1 11 5 Information Tab The Information tab is shown in Figure 1 7 Note the device revision could be different Figure 1 7 ALP Information Tab ...

Page 18: ...32A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide 1 11 6 HDMI Tab The HDMI tab is shown in Figure 1 8 Figure 1 8 ALP HDMI Tab ...

Page 19: ...ed May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide 1 11 7 Pattern Generator Tab The SER Pattern Generator tab is shown in Figure 1 9 Figure 1 9 ALP Pattern Generator Tab ...

Page 20: ...st 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide 1 11 8 Registers Tab The Registers tab is shown in Figure 1 10 Figure 1 10 ALP Registers Tab ...

Page 21: ...back Copyright 2018 2019 Texas Instruments Incorporated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide 1 11 9 Registers Tab Address 0x00 Selected Address 0x00 selected as shown in Figure 1 11 Note that the Value box will now show the hex value of that register Figure 1 11 ALP Device ID Selected ...

Page 22: ... the Address 0x00 content by bits Any register address displayed can be expanded Figure 1 12 ALP Device ID Expanded Any RW Type register can be written into by either writing the hex value into the Value box putting the pointer into the individual register bit s box by a left mouse click to put a check mark indicating a 1 unchecking the check mark indicating a 0 Click Apply to write to the registe...

Page 23: ...ure 1 13 Figure 1 13 ALP Scripting Tab The script window provides a full Python scripting environment that can be used for running scripts and interacting with the device in an interactive or automated fashion WARNING Directly interacting with devices either through register modifications or by calling the device support library functions can effect the performance and or functionality of the user...

Page 24: ...9A Q1EVM User s Guide 1 12 Troubleshooting ALP Software 1 12 1 ALP Loads the Incorrect Profile If ALP opens with the incorrect profile loaded the correct profile can be loaded from the USB2ANY Aardvark Setup found under the tools menu Figure 1 14 USB2ANY Setup 1 Highlight the incorrect profile in the Defined ALP Devices list and click the remove button Figure 1 15 Remove Incorrect Profile ...

Page 25: ...ck Copyright 2018 2019 Texas Instruments Incorporated DS90UH949A Q1EVM or DS90UB949A Q1EVM User s Guide 2 Find the correct profile under the Select a Daughter Board list highlight the profile and click Add Figure 1 16 Add Correct Profile 3 Click Ok and the correct profile should load Figure 1 17 Finish Setup ...

Page 26: ...EVM User s Guide 1 12 2 ALP Does Not Detect the EVM If the window shown in Figure 1 18 opens after starting the ALP software double check the hardware setup Figure 1 18 ALP No Devices Error 1 Check the device manager to make sure that the USB driver is installed There should be a HID compliant device under the Human Interface Devices as shown in Figure 1 19 Figure 1 19 Windows 7 ALP USB Driver ...

Page 27: ...then the software is most likely in demo mode When the ALP is operating in demo mode there is a Demo Mode indication in the lower left of the application status bar as shown in Figure 1 20 Figure 1 20 ALP in Demo Mode 3 Select the Preferences drop down menu and un check the Enable Demo Mode check mark to disable the demo mode Figure 1 21 ALP Preferences Menu After demo mode is disabled the ALP sof...

Page 28: ...ing is a list of typical test equipment that may be used to generate signals for the serializer inputs 1 Digital Video Source for generation of specific display timing such as Digital Video Processor or Graphics Controller GPU with HDMI or OpenLDI output 2 Any other signal generator video source This video generator may be used for video signal sources for DVI or DP 3 Any other signal video genera...

Page 29: ...rator Astrodesign www astro americas com Logic Analyzer keysight Technologies www keysight com Corelis CAS 1000 I2C E I2C Bus Analyzer and Exerciser Products www corelis com products I2C Analyzer htm Aardvark I2C SPI Host Adapter Part Number TP240141 www totalphase com products aardvark_i2cspi 1 15 Cable References For optimal performance TI recommends a Shielded Twisted Pair STP 24 AWG or larger ...

Page 30: ...RM 0 1 µF 16 V 10 X7R 0402 0402 GRM155R71C10 4KA88D MuRata C18 1 100uF CAP TA 100 µF 16 V 20 0 1 ohm SMD 7343 31 T495D107M016 ATE100 Kemet C19 C58 C66 C73 C80 C89 C92 7 47uF CAP CERM 47 µF 16 V 20 X5R 1210 1210 GRM32ER61C4 76ME15L MuRata C20 C28 C41 C45 C56 C115 C123 7 10uF CAP CERM 10 µF 10 V 10 X7R 0805 0805 GRM21BR71A1 06KE51L MuRata C22 1 3300pF CAP CERM 3300 pF 50 V 10 X7R 0402 0402 GRM155R71...

Page 31: ...3C104KAT2 A AVX C104 C106 C108 C109 4 0 1uF CAP CERM 0 1 µF 50 V 10 X7R 0402 0402 C1005X7R1H10 4K050BB TDK C110 1 0 012uF CAP CERM 0 012 µF 16 V 10 X7R 0402 0402 GRM155R71C12 3KA01D MuRata C116 C120 2 220pF CAP CERM 220 pF 50 V 1 C0G NP0 0603 0603 06035A221FAT2 A AVX C117 C118 2 30pF CAP CERM 30 pF 100 V 5 C0G NP0 0603 0603 GRM1885C2A30 0JA01D MuRata C119 1 2200pF CAP CERM 2200 pF 50 V 10 X7R 0603...

Page 32: ...il 16x2 Gold TH 16x2 Header TSW 116 07 G D Samtec J28 1 Header 100mil 4x1 Gold TH 4x1 Header TSW 104 07 G S Samtec J34 1 Connector Receptacle Mini USB Type B R A Top Mount SMT USB Mini Type B 1734035 2 TE Connectivity L3 1 4 7uH Inductor Shielded Drum Core Ferrite 4 7 uH 4 2 A 0 02 ohm SMD WE TPC XLH2 7440650047 Wurth Elektronik L4 L5 2 Coupled inductor 0 22 A 0 59 ohm SMD Inductor 1 2x1 2x2 0 mm ...

Page 33: ...R157 R158 R159 R160 R162 R163 R165 54 0 RES 0 5 0 063 W 0402 0402 ERJ 2GE0R00X Panasonic R21 1 4 99k RES 4 99 k 1 0 063 W 0402 0402 CRCW04024K99 FKED Vishay Dale R23 1 23 2k RES 23 2 k 1 0 063 W 0402 0402 CRCW040223K2 FKED Vishay Dale R25 1 12 1k RES 12 1 k 1 0 063 W 0402 0402 CRCW040212K1 FKED Vishay Dale R30 R31 R32 3 470 RES 470 5 0 063 W 0402 0402 CRCW0402470 RJNED Vishay Dale R35 1 1 0k RES 1...

Page 34: ... 0402 0402 CRCW0402137K FKED Vishay Dale R88 R97 R115 3 210k RES 210 k 1 0 063 W 0402 0402 CRCW0402210K FKED Vishay Dale R118 1 1 00k RES 1 00 k 1 0 1 W 0402 0402 ERJ 2RKF1001X Panasonic R161 1 49 9 RES 49 9 1 0 063 W 0402 0402 CRCW040249R 9FKED Vishay Dale R170 R171 2 33 RES 33 5 0 063 W 0402 0402 CRCW040233R 0JNED Vishay Dale R172 R179 R180 3 1 5k RES 1 5 k 5 0 063 W 0402 0402 CRCW04021K50 JNED ...

Page 35: ... 1 8 3 3 V Output 2 7 to 10 V Input 28 pin HTSSOP PWP 40 to 125 degC Green RoHS and no Sb Br PWP0028D TPS767D318PW P Texas Instruments U5 1 Socket DIP 8 Sleeve Pin 2 54 mm Pitch DIP 8 Body 10 16x10 16mm Pitch 2 54mm 110 13 308 41 001000 Mill Max U6 1 Automotive 210MHz HDMI to FPD Link III Bridge Serializer with HDCP RGC0064K VQFN 64 RGC0064K DS90UH949ATR GCRQ1 for Variant 001 Texas Instruments Aut...

Page 36: ...R 0603 0603 06031C103JAT2 A AVX C2 C5 C6 C10 C11 C13 0 10uF CAP CERM 10 µF 10 V 10 X7R 0805 0805 GRM21BR71A1 06KE51L MuRata C3 C7 C12 C14 0 0 1uF CAP CERM 0 1 µF 16 V 10 X7R 0402 0402 GRM155R71C10 4KA88D MuRata C4 C8 0 1uF CAP TA 1 µF 16 V 10 9 3 ohm SMD 3216 18 293D105X9016A 2TE3 Vishay Sprague C102 0 4 7uF CAP CERM 4 7 µF 16 V 10 X7R 0805 0805 GRM21BR71C4 75KA73L MuRata C103 C105 C107 0 0 1uF CA...

Page 37: ...10K0 FKED Vishay Dale R124 R135 R136 R140 R181 0 10k RES 10 k 5 0 1 W 0603 0603 CRCW060310K0 JNEA Vishay Dale R125 R126 R134 R137 R143 R183 R184 0 0 RES 0 5 0 1 W 0603 0603 CRCW06030000 Z0EA Vishay Dale R182 0 3 24k RES 3 24 k 1 0 063 W 0402 0402 CRCW04023K24 FKED Vishay Dale R185 0 0 51 RES 0 51 1 0 1 W AEC Q200 Grade 1 0603 0603 ERJ 3RQFR51V Panasonic R188 0 2 00k RES 2 00 k 1 0 063 W 0402 0402 ...

Page 38: ...Package Reference Part Number Manufacturer U12 0 Single Output Automotive LDO 750 mA Fixed 5 V Output 6 to 26 V Input 5 pin PFM KVU 40 to 125 degC Green RoHS and no Sb Br KVU0005A TL751M05QKVU RQ1 Texas Instruments Y1 0 OSC 12 288 MHz 3 3 Vdc SMD 14x9 8x4 7mm ECS 8FA3X 122 8 TR ECS Inc Y2 0 OSC 96 MHz 3 3 Vdc SMD SMD 4 Leads Body 7x5mm FXO HC736R 96 Fox Electronics Y3 0 OSC 148 5 MHz LVDS 3 3 V SM...

Page 39: ...18 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Appendix A SNLU232A August 2018 Revised May 2019 EVM PCB Schematics Figure A 1 Schematic Block Diagram ...

Page 40: ...9ATRGCRQ1 t variant 001 Appendix A www ti com 40 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Figure A 2 Schematic DS90UH949A Q1 and Power Decoupling ...

Page 41: ...www ti com Appendix A 41 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Figure A 3 Schematic MSP430 ...

Page 42: ...ix A www ti com 42 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Figure A 4 Schematic PDB IDx and MODE_SEL Switches ...

Page 43: ...ix A 43 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Figure A 5 Schematic HDMI HSD SMA I2C DDC CEC and GPIO I2S SPI Connectors ...

Page 44: ...Appendix A www ti com 44 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Figure A 6 Schematic LEDs ...

Page 45: ...ww ti com Appendix A 45 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Figure A 7 Schematic Audio Not Populated ...

Page 46: ...Appendix A www ti com 46 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Figure A 8 Schematic Power Regulators ...

Page 47: ...www ti com Appendix A 47 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated EVM PCB Schematics Figure A 9 Schematic Hardware ...

Page 48: ...18 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Appendix B SNLU232A August 2018 Revised May 2019 Board Layout Board Layers Figure B 1 Board Layer Top Overlay ...

Page 49: ...www ti com Appendix B 49 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Figure B 2 Board Layer Top Solder ...

Page 50: ...Appendix B www ti com 50 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Figure B 3 Board Layer Top ...

Page 51: ...www ti com Appendix B 51 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Figure B 4 Board Layer Ground 1 ...

Page 52: ...Appendix B www ti com 52 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Figure B 5 Board Layer Signal Layer ...

Page 53: ...www ti com Appendix B 53 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Figure B 6 Board Layer Power Split GND ...

Page 54: ...Appendix B www ti com 54 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Figure B 7 Board Layer Ground 2 ...

Page 55: ...www ti com Appendix B 55 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Figure B 8 Board Layer Bottom ...

Page 56: ...Appendix B www ti com 56 SNLU232A August 2018 Revised May 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Board Layout Figure B 9 Board Layer Bottom Solder ...

Page 57: ...rporated Revision History Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Original August 2018 to A Revision Page Added DS90UB949A Q1EVM information 5 Added content to the General Description section 5 Changed S4 S7 S8 BOM information 34 Changed U6 BOM information 35 ...

Page 58: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 59: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 60: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 61: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 62: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 63: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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