Texas Instruments DS320PR810-RSC-EVM, User Manual, Page: 5 / 32

2.3 DS320PR810 SMBus or I2C Register Control Interface
The DS320PR810 internal registers can be accessed through standard SMBus protocol. The DS320PR810
features two banks of channels, Bank 0 (Channels 0–3) and Bank 1 (Channels 4–7), each featuring a separate
register set and requiring a unique SMBus slave address. The SMBus slave address pairs (one for each channel
bank) are determined at power up based on the configuration of the EQ0_0/ADDR1 and EQ1_0/ADDR0 pins.
The pin state is read on power up, after the internal power-on reset signal is deasserted.
There are 16 unique SMBus slave address pairs (one address for each channel bank) that can be assigned to
the device by placing external resistor straps on the EQ0_0/ADDR1 and EQ1_0/ADDR0 pins as shown in
Table
2-3 . When multiple DS320PR810 devices are on the same SMBus interface bus, each channel bank of each
device must be configured with a unique SMBus slave address pair.
Table 2-3. DS320PR810 SMBus Address Map
ADDR1 Pin Level ADDR0 Pin Level
Bank 0: Channels 0-3:
7-Bit Address [HEX]
Bank 1 Channels 4-7:
7-Bit Address [HEX]
L0 L0 0x18 0x19
L0 L1 0x1A 0x1B
L0 L2 0x1C 0x1D
L0 L3 0x1E 0x1F
L0 L4 Reserved Reserved
L1 L0 0x20 0x21
L1 L1 0x22 0x23
L1 L2 0x24 0x25
L1 L3 0x26 0x27
L1 L4 Reserved Reserved
L2 L0 0x28 0x29
L2 L1 0x2A 0x2B
L2 L2 0x2C 0x2D
L2 L3 0x2E 0x2F
L2 L4 Reserved Reserved
L3 L0 0x30 0x31
L3 L1 0x32 0x33
L3 L2 0x34 0x35
L3 L3 0x36 0x37
L3 L4 Reserved Reserved
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DS320PR810-RSC-EVM User's Guide 5
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