background image

User’s Guide

DS160PT801X16EVM Riser Card Evaluation Module

ABSTRACT

The DS160PT801X16EVM is a 16-lane PCIe riser card board intended to be used for evaluation of the 
Texas Instruments DS160PT801 PCIe Gen4 retimer. The EVM uses the 1x16 Card Electromechanical (CEM) 
connector to enable quick system testing in a standard x16 socket and a standard PCIe endpoint. The evaluation 
board may be used with the SigCon Architect software program to provide register control and status information 
from the DS160PT801 devices. Contact a local Texas Instruments representative to obtain the SigCon Architect.

Figure 1-1. DS160PT801 EVM

Table of Contents

1 EVM Control and Configuration Information

........................................................................................................................

3

1.1 Retimer Pin Controls..........................................................................................................................................................

3

1.2 USB-to-SMBus Interface....................................................................................................................................................

4

1.3 PCIe PRSNT# Signal Control and Configuration...............................................................................................................

5

1.4 PCIe Reference Clock Control and Configuration..............................................................................................................

5

2 EVM Power

..............................................................................................................................................................................

7

2.1 EVM Current Sensing........................................................................................................................................................

8

3 SigCon Architect GUI

.............................................................................................................................................................

9

3.1 Setup and Installation.........................................................................................................................................................

9

3.2 Configuration Page..........................................................................................................................................................

10

3.3 Low-Level Page................................................................................................................................................................

11

3.4 EEPROM Page................................................................................................................................................................

12

3.5 Control Panel...................................................................................................................................................................

13

www.ti.com

Table of Contents

SNLU254A – NOVEMBER 2020 – REVISED JULY 2022

Submit Document Feedback

DS160PT801X16EVM Riser Card Evaluation Module

1

Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for DS160PT801X16EVM

Page 1: ...vices Contact a local Texas Instruments representative to obtain the SigCon Architect Figure 1 1 DS160PT801 EVM Table of Contents 1 EVM Control and Configuration Information 3 1 1 Retimer Pin Controls...

Page 2: ...shot 16 Figure 3 8 High Level Rx EQ DFE Page 16 Figure 3 9 High Level Page Tx FIR 17 Figure 3 10 Diagnostic Page Screenshot 18 Figure 3 11 Eye Monitor Page Screenshot 19 Figure 4 1 DS160PT801X16EVM PC...

Page 3: ...rely on the pin strap settings for configuration which may be modified using the shunt jumpers included with the EVM 1 1 Retimer Pin Controls The DS160PT801X16EVM is pre configured on power up to use...

Page 4: ...4 1 2 Connect EE_DAT to retimer enable EEPROM J45 1 2 Endpoint control of PRSNT 2 PCIe signal J46 1 2 Endpoint control of PRSNT 3 PCIe signal J47 1 2 Endpoint control of PRSNT 1 PCIe signal J48 1 2 En...

Page 5: ...useful if a certain width is desirable For example by inserting a shunt jumper in position 2 3 on header J45 will force the PRSNT status to represent a 1x4 mechanical link width 1 4 PCIe Reference Clo...

Page 6: ...K00334 CLK0 CDCE6214 25 MHz XTAL DS80PT801 CLK1 Y3 Y1 DS80PT801 A0 A1 J51 Test Point B0 B1 SMPs Y2 SMPs Net REFCLKP N_EP Straddle connector DNI R1 R2 DNI R47 R48 SELECT CLK1 SMPs DNI R95 R99 CEM conne...

Page 7: ...the EVM separately from the system power supply This can be used to help diagnose power supply issues and allow for pre configuration of the DS160PT801 through the SMBus interface before system power...

Page 8: ...delivered 12V_SENSE J60 Input 12 V supply to TPS548B22 VR VMEASURED 20 Input VR Current Amps 1 1P8 1 8 V supply to retimer 0 U2 VMEASURED 20 Retimer 1 8 V current consumption in Amps 2 P2A 1 17 V sup...

Page 9: ...e framework the DS160PT801 product profile may be added The step by step setup instructions below show be followed to complete the installation of the software and prepare the DS160PT801X16EVM for eva...

Page 10: ...ink width manager Follower Address Dropdown specifies the SMBus address of the link follower Toggle LED Button can toggle an onboard LED and can be used to confirm a successful connection Apply Button...

Page 11: ...field will be written to Write Register Button issues an SMBus write of the data listed in the data field at the current address using the bit mask indicated in the Mask Value field Broadcast Button b...

Page 12: ...and updates the GUI with its contents Write to EEPROM Button writes the EEPROM configuration that is currently active in the GUI to the EEPROM device Load From Hex File Button opens a file explorer w...

Page 13: ...onfiguration set s data Active Device Dropdown changes the active device for the Load From Device and Write to Device commands Field Description Table shows the register map information about the curr...

Page 14: ...bled in the High Level page when modifying the Rx Tx EQ settings the Diagnostic page and Eye Monitor pages Load From File Button allows a user to load a previously saved configuration file Save to Fil...

Page 15: ...Initialize Button applies the Bifurcation and Retimer Present changes to the retimer over SMBus communication It is important to note than any SMBus settings affecting PCIe link configuration like th...

Page 16: ...s includes the Link Lane number and orientation of the data flow Edit Field Visibility Button allows a user to show or hide different columns within the channel status table Figure 3 8 High Level Rx E...

Page 17: ...kbox enables a user to finely control the boost stage settings for the CTLE Reset CTLE Button resets the CTLE Index to 0 Load CTLE Button loads a saved pre configured CTLE value Save as CTLE Button sa...

Page 18: ...n generator with the specified pattern type and datarate If using a PCIe compliance pattern it is possible to also force a specific PCIe preset value for the transmitted signal Pattern Type Dropdown m...

Page 19: ...re stops a continuous capture Recompute HEO VEO performs a quick measurement of the HEO and VEO of a channel This method uses the same technique on the high level device status page to calculate the H...

Page 20: ...ts and reduces losses where high dynamic currents are present Layer 3 and Layer 4 in the stackup are dedicated to the high speed analog and digital supply rails Both of these rails are nominally 1 1 V...

Page 21: ...V levels to the attached endpoint and regulator inputs As with any Serdes hardware design power distribution is important to the overall device performance To ensure optimal voltage levels at the ret...

Page 22: ...igh current analog and digital decoupling uses Top and Bottom layer capacitors to optimize the overall frequency response of the decoupling solution Figure 4 5 Decoupling Solution Frequency Response P...

Page 23: ...perform well Placing the high current supplies close to the top layer surface ensures the lowest inductance possible to the supply plane and ultimately to the device itself Figure 4 6 PCB Top Layer ww...

Page 24: ...ision History Rev Notes Approved by ECN Approved Date N A N A N A N A N A Figure 5 1 Schematic Cover Sheet DS160PT801X16EVM Schematic www ti com 24 DS160PT801X16EVM Riser Card Evaluation Module SNLU25...

Page 25: ...l width 1pF C235 43 R75 RSVD1 1pF C236 43 R76 RSVD2 1pF C237 43 R77 RSVD3 1pF C238 43 R78 RSVD4 1pF C239 43 R79 RSVD5 GND 1pF C240 43 R80 CLKREQ 1pF C241 43 R81 PRSNT2_1 1pF C242 43 R82 PWRBRK 1pF C24...

Page 26: ..._0 RX_DET0 1 2 3 4 5 6 7 8 J6 TSW 104 07 G D GND V1P8_0 MODE0 AD0_0 AD1_0 WIDTH0 1 2 3 4 5 6 J7 TSW 103 07 G D GND V1P8_0 1 2 3 4 5 6 J8 TSW 103 07 G D GND V1P8_0 1 2 3 4 5 6 J9 TSW 103 07 G D GND V1P...

Page 27: ...e connect at DS160PT801 RT0 P2_A Supply should be differential with GND trace 1 00 R129 0 1uF C306 0 1uF C307 0 1uF C324 1uF C308 1uF C312 1uF C323 10nF C333 10nF C335 47uF C316 3 3uF C317 0 47uF C318...

Page 28: ...3IPWR U5 1 1V INA Output GND 1uF C90 1uF C79 0 1uF C91 0 1uF C80 600mA maximum V1P1A_0 47uF C87 L3 4 A P2_D_0 1 8V Reg Output GND 0 1uF C86 130mA maximum INA210AIDCKR GND 2 IN 4 IN 5 REF 1 V 3 OUT 6 U...

Page 29: ...20 INA253A3IPWR U8 1 1V INA Output GND 1uF C178 1uF C167 0 1uF C179 0 1uF C168 600mA maximum V1P1A_1 47uF C175 L5 4 A P2_D_1 1 8V Reg Output GND 0 1uF C174 130mA maximum INA210AIDCKR GND 2 IN 4 IN 5...

Page 30: ...CLK_EP_N 10uF C2 10uF C1 10uF C3 10uF C8 To LMK00334 CLK input GND 0 R12 DNI VDD_CDC GND C_CLK_0_P C_CLK_0_N Y1_0_P Y1_0_N 4 7k R10 CDCE6214WRGERQ1 VDD_REF 3 VDD_VCO 24 VDDO_12 16 VDDO_34 15 REFSEL 4...

Page 31: ...LMK_3P3 LMK_3P3 LMK_3P3 GND GND V3P3_F LMK_EP_P V3P3_F V3P3_F LMK_EP_P LMK_EP_P LMK_EP_N LMK_P LMK_EP_N LMK_P LMK_N LMK_N RCLK_P RCLK_N RCLK_P RCLK_N GND GND LMK_EP_N RCLK_N RCLK_P LMK_P LMK_N REFCLK...

Page 32: ...58 P7 6 TB0 4 59 P7 7 TB0CLK MCLK 60 VSSU 61 PU 0 DP 62 PUR 63 PU 1 DM 64 VBUS 65 VUSB 66 V18 67 AVSS2 68 P5 2 XT2IN 69 P5 3 XT2OUT 70 TEST SBWTCK 71 PJ 0 TDO 72 PJ 1 TDI TCLK 73 PJ 2 TMS 74 PJ 3 TCK...

Page 33: ...0 X5R 0402 0402 GRM155R60J475ME87D MuRata C15 C26 C48 C59 C103 C114 C136 C147 C188 C191 C195 C198 C201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 C212 C213 C214 C215 C216 C218 C219 C220 C221 C2...

Page 34: ...5R 0805 0805 EMK212BBJ226MG T Taiyo Yuden C302 C327 2 100 F CAP Tantalum Polymer 100 F 20 V 20 0 055 7 3x4 3 mm SMD 7 3x4 3 mm 20TQC100MYF Panasonic C303 C304 C309 C310 C311 C326 6 22 F CAP CERM 22 F...

Page 35: ...unt SMT USB Mini Type B 1734035 2 TE Connectivity J57 1 Conn SATA PL 22 POS Solder RA SMD 22 Terminal 1 Port T R CONN_SMT _SATA 10101788 002CLF Amphenol L1 L2 L4 L6 L7 5 80 Ferrite Bead 80 at 100 MHz...

Page 36: ...0733RL Yageo America R110 R111 2 33 RES 33 5 0 063 W AEC Q200 Grade 0 0402 0402 CRCW040233R0JNED Vishay Dale R112 1 1 5k RES 1 5 k 5 0 063 W AEC Q200 Grade 0 0402 0402 CRCW04021K50JNED Vishay Dale R1...

Page 37: ...H J13 SH J15 SH J16 SH J17 SH J18 SH J19 SH J20 SH J21 SH J22 SH J23 22 1x2 Shunt 100mil Flash Gold Black Closed Top 100mil Shunt SPC02SYAN Sullins Connector Solutions U1 1 CDCE6214WRGERQ1 RGE0024P VQ...

Page 38: ...Texas Instruments Y1 1 Crystal 25 MHz 8 pF SMD 3 2x0 75x2 5 mm NX3225GA 25 000M STD CRG 2 NDK Y2 1 Crystal 24 MHz 18 pF SMD ABM3 ABM3 24 000MHZ D2Y T Abracon Corporation FID1 FID2 FID3 FID4 FID5 FID6...

Page 39: ...t version Changes from Revision November 2020 to Revision A July 2022 Page First public release of user s guide 3 www ti com Revision History SNLU254A NOVEMBER 2020 REVISED JULY 2022 Submit Document F...

Page 40: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 41: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 42: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 43: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 44: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 45: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

Reviews: