Texas Instruments DS160PR810EVM-RSC, User Manual, Page: 7 / 33

2.7 DS160PR810 EVM Global Controls
Table 2-7 shows DS160PR810EVM-RSC global controls that affect all devices on the board.
Table 2-7. EVM Global Controls
COMPONENT NAME FUNCTION / DESCRIPTION
J1 3x2 Header
MODE control tied to MODE pins of all four DS160PR810 devices on the EVM
L0: All devices set to Pin Mode (Default)
L1: All devices set to SMBus, I2C Maseter Mode
L2: SMBus, I2C Slave Mode
L3: Reserved
J2 3x2 Header
RX DET control tied to RX DET pins of all four DS160PR810 devices on the EVM
L0: RX Detect state machine disabled on all devices
L1: RX Detect state machine enabled on all devices (3 valid detections needed)
L2: RX Detect state machine enabled on all devices (2 valid detections needed)
L3: RX Detect state machine enabled on all devices (1 valid detection needed) -
Default
J3 5x2 Header
SMBus, I2C interface. All four DS160PR810 devices on the EVM are on the same
bus and can be accessed through this interface.
J4 3x1 Header
PWDN control tied to PD1 and PD2 pins of all four DS160PR810 devices on the
EVM PWDN tied to GND: All devices enabled (Default) PWDN tied to 3.3V_REG:
All devices disabled.
PWDN floating: Tie PCIe system PRSNT signal to PWDN using J6 for the PWDN
control (optional for PCIe use case)
J5 3x1 Header
Access point to the WP (write protect) pin of the onboard EEPROM devices WP
tied to GND: I2C Access to the EEPROM enabled WP floating: I2C Access to the
EEPROM disabled (default)
J6 2x1 Header
Alternative PWDN Control PWDN floating: Use J3 for the PWDN control PWDN
tied to PRSNT: PRSNT signal controls PWDN (optional for PCIe use case)
J7, J8, J9, J10 3x1 Headers
PCIe PRSNT Signal Controls Tie pins 1-2 on J7, J8, J9, and J10: Allow support
any PCIe bus width (default) Tie pins 2-3 of J7, leave J8, J9, and J10 floating:
Force x1 PCIe bus width Tie pins 2-3 of J8, leave J7, J9, and J10 floating: Force x4
PCIe bus width Tie pins 2-3 of J9, leave J7, J8, and J10 floating: Force x8 PCIe
bus width Tie pins 2-3 of J10, leave J7, J8, and J9 floating: Force x16 PCIe bus
width
J11 2x1 Header
Onboard regulator input. Apply 12 V when using the EVM as a standalone system.
DO NOT APPLY power if plugging the EVM into a system as the power is provided
through the gold finger connector (CONN1).
J12 2x1 Header Access point to the GND reference
J13 2x1 Header Onboard 3.3-V output
www.ti.com Description
SNLU273 – DECEMBER 2020
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