EVM Layout
13
SNLU142A – May 2014 – Revised January 2016
Copyright © 2014–2016, Texas Instruments Incorporated
DS110DF111EVM Evaluation Board
6
EVM Layout
and
show the board layout for the DS110DF111EVM. The EVM uses simple 100 mil
headers to control the output signal integrity functions. The DS110DF111EVM is very compact and low
power, the board traces have been designed for connection to standard 50
Ω
test equipment and cables.
The QFN package offers an exposed thermal pad to enhance electrical and thermal performance (this pad
must be soldered to the copper landing on the PCB).
Figure 9. Top Assembly Layer
Figure 10. Bottom Assembly Layer