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2
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4
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5
5
6
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D
D
C
C
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Main Circuit
5/24/2018
SENS036A_Main.SchDoc
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DRV505x Angle Sense EVM
Project Title:
Designed for:
Public Release
Assembly Variant:
001
© Te xas Instruments
2018
Drawn By:
Engineer:
H. Munikoti
H.Munikoti
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable f or your application or fit for any particular purpose, or will operate in an im plementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm th e system functionality for your application.
Version control disabled
SVN Rev:
SENS036
Number:
Rev:
A
TID #:
N/A
Orderable:
DRV5055-ANGLE-EVM
GND
VCC
GND
GND
GND
GND
GND
GND
GND
VCC
1uF
C20
0
R9
RST
TEST
GND
GND
GND
GND
100
R1
100
R2
100
R3
100
R4
35V
1.5uF
C5
35V
1.5uF
C6
35V
1.5uF
C7
35V
1.5uF
C8
BUTTON
VCC
GND
10.0k
R7
GND
GND
VCC
S1
GND
GND
0
R11
TP1
DNP
TP2
DNP
TP3
DNP
TP4
DNP
SN74LVC1G17DCKT
4
2
U7A
SN74LVC1G17DCKT
VCC
5
GND
3
NC
1
U7B
0.1uF
C15
0.1uF
C4
0.1uF
C3
0.1uF
C2
0.1uF
C1
10uF
C14
TLV75533PDBVR
OUT
5
GND
2
NC
4
EN
3
IN
1
U10
VCC
VCC
VCC
VCC
VCC
TEST
RST
BUTTON
GND
GND
GND
GND
COM1
1
NC
2
NC
3
NC
4
4E
5
4D
6
4C
7
DP3
8
3E
9
3D
10
3C
11
DP2
12
2E
13
2D
14
2C
15
DP1
16
1E
17
1D
18
1C
19
1B
20
1A
21
1F
22
1G
23
2B
24
3G
32
NC
33
4B
34
4A
35
4F
36
4G
37
NC
38
2A
25
2F
26
2G
27
L
28
3B
29
3A
30
3F
31
NC
39
COM1
40
U11
VI-401-DP-RC-S
DP3
4C
4D
4E
DP2
3C
3D
3E
DP1
2C
2D
2E
1B
1C
1D
1E
COM
4G
4F
4A
4B
3G
3F
3A
3B
2G
2F
2A
2B
1G
1F
1A
COM
COM
CS
4
SDO
3
SCLK
2
DVDD
1
GND
8
AVDD
7
AINP
6
AINM
5
ADS7042IDCUR
U8
CS
4
SDO
3
SCLK
2
DVDD
1
GND
8
AVDD
7
AINP
6
AINM
5
ADS7042IDCUR
U9
10uF
C21
GND
GND
GND
1uF
C19
1uF
C18
GND
1uF
C16
0.1uF
C24
0.1uF
C26
0.1uF
C25
0.1uF
C23
GND
0.1uF
C9
GND
MUX0
MUX1
1uF
C17
V+
1
2
3
IN1
4
5
GND
6
7
IN2
8
9
10
TS3A24159DGSR
U5
OPA2314AIDGK
1
3
2
4
8
U6A
OPA2314AIDGK
7
5
6
4
8
U6B
GND
1500pF
C12
1500pF
C13
GND
GND
0.1uF
C10
GND
VCC
VCC
VCC
VCC
VCC
MUX1
D4
UCB0 bus is SPI master, UCA0 is a slave
VCC
VCC
P4.7/R13
1
P4.6/R23
2
P4.5/R33
3
P4.4/LCDCAP1
4
P4.3/LCDCAP0
5
P4.2/XOUT
6
P4.1/XIN
7
DVSS
8
DVCC
9
RST/NMI/SBWTDIO
10
TEST/SBWTCK
11
P4.0/TA1.1
12
P8.3/TA1.2
13
P8.2/TA1CLK
14
P8.1/ACLK/A9
15
P8.0/SMCLK/A8
16
P1.7/TA0.1/TDO/A7
17
P1.6/TA0.2/TDI/TCLK/A6
18
P1.5/TA0CLK/TMS/A5
19
P1.4/MCLK/TCK/A4/VREF+
20
P1.3/UCA0STE/A3
21
P1.2/UCA0CLK/A2
22
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
23
P1.0/UCA0TXD/UCA0SIMO/A0/Veref-
24
P5.7/L39
25
P5.6/L38
26
P5.5/L37
27
P5.4/L36
28
P5.3/UCB0SOMI/UCB0SCL/L35
29
P5.2/UCB0SIMO/UCB0SDA/L34
30
P5.1/UCB0CLK/L33
31
P5.0/UCB0STE/L32
32
P2.7/L31
33
P2.6/L30
34
P2.5/L29
35
P2.4/L28
36
P2.3/L27
37
P2.2/L26
38
P2.1/L25
39
P2.0/L24
40
P6.7/L23
41
P6.6/L22
42
P6.5/L21
43
P6.4/L20
44
P6.3/L19
45
P6.2/L18
46
P6.1/L17
47
P6.0/L16
48
P3.7/L15
49
P3.6/L14
50
P3.5/L13
51
P3.4/L12
52
P3.3/L11
53
P3.2/L10
54
P3.1/L9
55
P3.0/L8
56
P7.7/L7
57
P7.6/L6
58
P7.5/L5
59
P7.4/L4
60
P7.3/L3
61
P7.2/L2
62
P7.1/L1
63
P7.0/L0
64
MSP430FR4133IPMR
U12
GND
4E
DP3
4C
4D
DP2
3C
3D
3E
2E
DP1
2C
2D
1B
1C
1D
1E
COM
2G
2F
2A
2B
1G
1F
1A
3G
3F
3A
3B
4G
4F
4A
4B
1
2
D1
10.0k
R5
1
2
D2
10.0k
R12
1
2
D3
10.0k
R13
1
2
D4
10.0k
R14
VCC
D1
D2
D3
D4
GND
100
R15
1uF
C27
MUX0
D3
D1
D2
TP6
DNP
TP7
DNP
TP8
DNP
GND
TP9
DNP
TP12
DNP
TP10
DNP
TP11
DNP
TP13
TP5
PWM1
PWM2
PWM1
PWM2
VBUS
1
D-
2
D+
3
ID
4
GND
5
6
7
8
1
1
1
0
9
J1
GND
DRV5055A1QLPGM
VCC
1
OUT
3
GND
2
U2
DRV5055A3QDBZT
OUT
2
VCC
1
GND
3
U1
DRV5055A1QLPGM
VCC
1
OUT
3
GND
2
U4
DRV5055A3QDBZT
OUT
2
VCC
1
GND
3
U3
1500pF
C22
47k
R10
309
R8
309
R6
5
4
1
2
3
J2
Schematics, PCB Layout, and Bill of Materials
10
SLYU048 – July 2018
Copyright © 2018, Texas Instruments Incorporated
DRV5055-ANGLE-EVM
4
Schematics, PCB Layout, and Bill of Materials
4.1
Schematics
Figure 5. Schematic of DRV5055-ANGLE-EVM
