Texas Instruments DRA76xP-ACD, User Manual, Page: 26 / 38

SoC
Mux
C
B1
B2
NOR
Memory
EMMC
Memory
MMC2
MMC2_CLK, _CMD,_DA{7:0]
GPMC
GPMC_A[27:19], _CS[1]
GPMC_A[27:19],_CS[1]
CBTLV16212
A1=B1 or A1=B2
A1
Copyright © 2017, Texas Instruments Incorporated
SoC
Mux
B
B1
B2
NAND
Memory
FPD-Link
Panel
DIP Switch
(SYSBOOT)
NOR Memory
VOUT3
VOUT3_CLK, _VS, _HS,
_DE, _D[23:0], GPIO2_2
GPMC
GPMC_A[12:0], _AD[15:0]
GPMC_AD[15:0],
_A[12:0],_CS[3]
SN74CBTLV16212
A1=B1 or A1=B2
A1
Copyright © 2017, Texas Instruments Incorporated
Signal Multiplex Logic
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26 SPRUII5A – December 2017 – Revised November 2018
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DRA77xP/DRA76xP-ACD CPU EVM Board
Figure 8. Mux Diagram for GPMC/VOUT3
4.3 GPMC/EMMC Selection (Mux C)
Table 18 shows part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• Memory Bus (GPMC): A[27:19], CS[1]
• EMMC Memory (MMC2): CLK, CMD, D[7:0]
Table 18. SoC Pinmux for GPMC/EMMC
Pad Name Function 1 Function 2
gpmc_a[19] GPMC gpmc_a[19] MMC2 mmc2_dat[4]
gpmc_a[20] GPMC gpmc_a[20] MMC2 mmc2_dat[5]
gpmc_a[21] GPMC gpmc_a[21] MMC2 mmc2_dat[6]
gpmc_a[22] GPMC gpmc_a[22] MMC2 mmc2_dat[7]
gpmc_a[23] GPMC gpmc_a[23] MMC2 mmc2_clk
gpmc_a[24] GPMC gpmc_a[24] MMC2 mmc2_dat[0]
gpmc_a[25] GPMC gpmc_a[25] MMC2 mmc2_dat[1]
gpmc_a[26] GPMC gpmc_a[26] MMC2 mmc2_dat[2]
gpmc_a[27] MMC2 mmc2_dat[3]
gpmc_cs[1] MMC2 mmc2_cmd
Mux C: Selects between on board NOR memory and EMMC memory. The selection is made using dip
switch setting (SW6 pin 3), or can be set using the IO expander #3, bits P15:14. If booting from EMMC,
the DIP Switch SW6 position 3 is used to select interface.
Figure 9. Mux Diagram for GPMC/EMMC