Texas Instruments DRA76xP-ACD, User Manual, Page: 13 / 38

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13 SPRUII5A – December 2017 – Revised November 2018
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DRA77xP/DRA76xP-ACD CPU EVM Board
Table 6. SoC Boot Mode Switch Settings
SoC Interface
(Internal System Boot Input)
CPU Board Net
DIP Switch Ref Destination
Position Number Connections Factory Settings
GPMC_AD0 (sysboot0) GPMC_D00 SW3.P1 ON
GPMC_AD1 (sysboot1) GPMC_D01 SW3.P2 OFF
GPMC_AD2 (sysboot2) GPMC_D02 SW3.P3 ON
GPMC_AD3 (sysboot3) GPMC_D03 SW3.P4 OFF
GPMC_AD4 (sysboot4) GPMC_D04 SW3.P5 ON
GPMC_AD5 (sysboot5) GPMC_D05 SW3.P6 OFF
GPMC_AD6 (sysboot6) GPMC_D06 SW3.P7 OFF
GPMC_AD7 (sysboot7) GPMC_D07 SW3.P8 OFF
GPMC_AD8 (sysboot8) GPMC_D08 SW4.P1 ON
GPMC_AD9 (sysboot9) GPMC_D09 SW4.P2 OFF
GPMC_AD10 (sysboot10) GPMC_D10 SW4.P3 OFF
GPMC_AD11 (sysboot11) GPMC_D11 SW4.P4 OFF
GPMC_AD12 (sysboot12) GPMC_D12 SW4.P5 OFF
GPMC_AD13 (sysboot13) GPMC_D13 SW4.P6 OFF
GPMC_AD14 (sysboot14) GPMC_D14 SW4.P7 OFF
GPMC_AD15 (sysboot15) GPMC_D15 SW4.P8 ON
In addition to SoC boot settings, EVM resources must also be set for the desired boot interface. Table 7
shows the boot interfaces that require selection. DIP switch SW6 is used to configure the various boot
memories.
Table 7. Board Controls for Booting Options
Signals Description DIP Switch
Factory
Settings
NAND_BOOTn ON = Enable GPMC_nCS0 for NAND flash boot SW6.1 OFF
NOR_BOOTn ON = Enable GPMC_nCS0 for NOR flash boot SW6.2 OFF
MMC2_BOOT ON = Enable MMC2 Interface for eMMC flash boot SW6.3 OFF
SEL_VCC_CSI2_IO OFF = Selects 3.3 V IO for CSI2 imager interfaces (Leopard image
and Samtec)
ON = Selects 1.8 V IO for CSI2 Interfaces SW6.4 ON
UART_SEL1_3 OFF = Selects UART3 for terminal USART
ON = Selects UART1 for terminal USART SW6.5 ON
MCASP1_ENn ON = Enable signal paths to COMx module SW6.6 OFF
SW_VPP_EN ON = Enable VPP supply to SOC
(also requires IO Exp bit to be set) SW6.5 OFF
PCI_RESET_SEL OFF = PCIe device may reset SoC
ON = SoC may reset the PCIe device SW6.8 OFF
GPMC_WPN ON = Enable write protection of NAND Flash SW6.9 OFF
I2C_EEPROM_WP High = Enable write protection of Board identification EEPROM SW6.10 OFF
1. Routing control for GPMC_nCS0 is “shared” between NOR & NAND Flash memories. Ensure that only
one DIP switch, SW8.P1 or SW8.P2, is ever set to “ON” state at any one time so that GMPC_nCS0 is
only connected to one memory. Failure to adhere to this requirement will cause NOR & NAND memory
data bus contention.
2. UART3 peripheral boot and terminal access requires a on-board resistor modification.