Texas Instruments DRA76xP-ACD, User Manual, Page: 11 / 38

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11 SPRUII5A – December 2017 – Revised November 2018
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DRA77xP/DRA76xP-ACD CPU EVM Board
Table 5 summarizes the reset signals.
Table 5. Reset Signals Structure
Reset Type Reset Signal Sources Comments
Power-On Reset (as whole system reset) CPU_POR_RESETn PORn push button reset
PCI_PORz PCIe inbound reset
PMIC_RESET_OUT Power on reset from power ICs
Warm Reset CPU_RESETn Warm push button reset
EMU_RSTn Reset from Emulator
PMIC Power On Reset PMIC_RESET_IN PMIC reset input
Processor Reset Out RSTOUTn Reset Output from processor to system,
PMIC (warm reset input)
3.4 Clocks
The SoC supports up to two primary clock inputs. The device clock (OSC0) is sourced with 20 MHz clock.
The auxiliary clock (OSC1) is sourced with a 22.5792 MHz clock. Both clocks are sourced from a clock
synthesizer (CDC925).
In addition to the SoC clock inputs, the EVM includes other clock sources. 25 MHz clocks are provided to
Ethernet PHY(s) and 100 MHz clock is sourced for miniPCIe. Both the SoC and Ethernet clocks are
sourced from a clock synthesizer (CDC925).
3.5 Memory
3.5.1 SDRAM Memory
The EVM includes 4GBytes of DDR3L memory and can operate at clock speeds up to 667 MHz (DDR3-
1333). The SoC supports two separate memory interfaces, EMIF1 and EMIF2, and the memory is
distributed evenly between the banks (2 Gbyte each). ECC is supported on EMIF1 only.
While supporting the same amount of memory, the two EMIF interfaces are implemented differently.
EMIF1 is configured with two memory devices of 8Gbit each (x16b devices) plus ECC. EMIF2 is
configured with four devices of 4 Gbit each (x8b devices). This configuration is done to provide different
reference PCB layout/routing for the different examples.
• DDR3L device used: Micron MT41K512M8RH-125-AA:E (4x8 bit @ 4 Gbit/ea) (or equivalent).
• DDR3L device used: Micron MT41K512M16HA-125:A (2x16 bit @ 8 Gbit/each) (or equivalent).
• EEC device used: Micron MT41K512M8RH-125-AA:E (1x8 bit @ 4 Gbit) (or equivalent).
The DDR3L power is generated from the SoC power solution, specifically the TPS54116. Its output
voltage is set to 1.35 V. It uses ‘fly-by’ topology with VTT termination. VTT supply is generated by the
same TPS54116 device, which includes a sink/source termination regulator.
3.5.2 QSPI Flash Memory
As a primary non-volatile boot device, the EVM includes 256 Mbit of Quad-SPI Flash memory. The device
is support on chip select zero of the QSPI interface. The interface can be configured to support either
serial mode (1x) or quad mode (4x).
• QSPI device used: Spansion S25FL256S
Booting from the QSPI Flash memory is supported on the EVM. No EVM configuration is required as the
QSPI flash is enabled by default. Ensure the correct SoC boot mode is set using the SYS_BOOT switches
(SW3, SW4).