Texas Instruments DRA72 Series, User Manual, Page: 27 / 39

NOR Memory
EMMC
Memory
MMC2
MMC2_CLK, _CMD, _DA[7:0]
Mux
C
A1 B1
B2
GPMC_A[27:19], _CS[1]
SoC
GPMC
GPMC_A[27:19], _CS[1]
CBT16212
A1=B1 or A1=B2
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Signal Multiplex Logic
27 SPRUIB9 – December 2016
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DRA72x EVM CPU Board User's Guide
Mux C: Selects between NOR memory and EMMC memory, as shown in Figure 12 . The selection is made
using the IO expander #3, and bits P15 and P14. If booting from EMMC, the DIP Switch SW5 position 3 is
used to select interface (by default).
Figure 12. Mux Diagram for GPMC and EMMC
4.4 VIN2A Selection (Mux E)
Figure 13 is part of the SoC pinmux table for VIN2A. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• Video Input Port (VIN2A): CLK, HSYNC, VSYNC, DE, D[9:0]
Figure 13. SoC Pinmux for VIN2A and EMU