Texas Instruments DRA72 Series, User Manual, Page: 26 / 39

NAND
Memory
FPD Link
Transmitter
VOUT3
VOUT3_CLK, _VS, _HS, _DE,
_D[23:0]
Mux
B
A1 B1
B2
GPMC_A[12:0], _AD[15:0]
SoC
GPMC
GPMC_A[12:0], _AD[15:0]
CBT16214
A1=B1 or A1=B2 or A1 = B3
B3
NOR Memory
DIP Switch
(SYSBOOT)
VIN1A
VIN1A_CLK, _VS, _HS, _DE, _D[23:0]
Expansion
Connector
Signal Multiplex Logic
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DRA72x EVM CPU Board User's Guide
Mux B: Selects between NOR/NAND memories, FPD Linkl for video, and expansion, as shown in
Figure 10 . The selection is made using the IO expander #2, and bits P7 and P0. The defaults are set to
enable GPMC to NOR/NAND memories, required for SYSBOOT mode latching.
Figure 10. Mux Diagram for GPMC/VIN1/VOUT3
4.3 GPMC and EMMC Selection (Mux C)
Figure 11 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• Memory Bus (GPMC): A[27:19], CS1
• EMMC Memory (MMC2): CLK, CMD, D[7:0]
Figure 11. SoC Pinmux for GPMC/EMMC