Hardware
16
SPRUIB9 – December 2016
Copyright © 2016, Texas Instruments Incorporated
DRA72x EVM CPU Board User's Guide
3.12.2
LCD Touch Panel
The EVM supports a LCD panel interface for supporting video output to a LCD panel. The SoC VOUT1
resource is used drive up to 24b RGB data to interface. The interface supports resource connections for
interfacing with a touch panel for advanced user interfaces. These include a control bus (I2C1) and
interrupt for touch indications (GPIO)
An LCD panel is not included with the CPU EVM, but can be ordered and included as part of an assembly
kit.
Connector used: Molex
3.12.3
FPD-Link III Output and Panel
The EVM includes a FPD-Link III parallel-to-serial interface on VOUT3. It supports up to 24bits of data and
can operate at pixel rates up to 85 MHz. The interrupt is supported to enable back-channel
communication, typically needed if supporting touch screen. The transceiver is configured using I2C (port
5, 0x1B).
Serializer device used: Texas Instruments DS90UH925Q
Connector used: Automotive HSD Connector, right-angle plug for PCB, Rosenberger D4S20D-40ML5-Z.
3.13 Video Input
3.13.1
Parallel Imaging
Parallel video input is supported through connections from external sensors and transceivers. The SoC
port VIN2A is routed to a connector interface designed to mate with camera sensors from Leopard
Imaging. This approach provides flexibility for customers to select from a variety of available modules,
while also supporting connections of custom solutions. The attached module can be configured using
either I2C (port 5) or SPI (port 1).
Connector used: FPC 36 position, 0.5 mm, Molex 052559-3679.
3.13.2
Serial Imaging
Serial video input is supported through connections from external sensors and transceivers. The SoC port
CSI2-0 is routed to connector interfaced designed to mate with camera sensors from Leopard Imaging.
This approach provides flexibility for customers to select from a variety of available modules. Both serial
ports (CSI2-0 and CSI2-1) are routed to an expansion connector for supporting a variety of custom
solutions. Both interfaces support additional signals for the control and configuration of the attached
modules. These interfaces (I2C port 5, SPI port 1) are translated to 1.8-V IO (with resistor option to leave
at 3.3-V IO).
LI Connector used: FPC 36 position, 0.5 mm, Molex 052559-3679
Connector used: Samtec QSH-020-01-L-D-DP-A
3.14 PCIe
The EVM supports a PCIe (single-lane) interface for connecting with a variety of external modules. A
second lane is available with a component modification (FL2, FL3). An on-board clock generator
CDCM9102 provides the 100-MHz reference clock to both the SoC and attached modules. The EVM
support two different PCIe reset configurations, select using DIP switch SW5 position 8. The default
setting of ON lets SoC reset the PCIe peripheral. The switch setting of OFFlets the PCIe peripheral reset
the SoC.