3.3 Clock Selection – DP83TD510E
3.3.1 50 MHz Reference Clock for DP83TD510E in RMII Slave Mode
• Remove R135, R137, R149
• Populate R143, R25
3.3.2 External Clock
• Remove R135
• Populate R134, J7
• Provide External Clock to SMA at J7
3.3.3 On-Board 25 MHz crystal
• Remove R134, R143, R25
• Populate R135, R137
3.4 SMI Connection
In Media Converter configurations, the MDIO/MDC lines of the DP83TD510E and DP83822I are tied together.
Both PHYs can be accessed simultaneously. The DP83TD510E has been set to PHY address 00 and the
DP83822I has been set to PHY address 05.
• Connect micro-USB to J4
• For direct access to MDIO, MDC lines, populate headers at J22, J23, on DP83TD510E and/or J13, J28 on
DP83822I
3.5 Cable Assembly
• Plug a CAT5, CAT5E, or CAT6 cable into the RJ45 connector J2
– Connect the far-end of the Ethernet cable to a 10BASE-TX capable PHY
• Plug a Single-Pair-Ethernet wires into the terminal block J1 as labeled
– Connect the far-end of the cable to a 10BASE-T1L capable PHY
3.6 LED Indication
• Look for LED_0 and LED_1 to illuminate when a link is successfully established
• Look for Green LED to illuminate on the RJ45 connector J2 when a link is successfully established (in media
convertor mode)
• LED_1 will blink for TX/RX activity
3.7 Serial Management Interface
The DP83TD510E-EVM supports SMI (MDIO/MDC) through J22, J23 and includes an onboard MSP430F5529
for USB-2-MDIO control.
Notes:
• DP83TD510E default PHY_ID is 0
• DP83822 default PHY_ID is 5
• PHY IDs can be changed through bootstrap options found in the data sheet
3.8 Configuration Options
3.8.1 Bootstrap Options
Some DP83TD510E and DP83822 configurations can be done through bootstrap options. Options can be
selected with jumpers or resistor population. Refer to the data sheets for bootstrap options and the schematic
and layout sections of this User’s Guide for resistor locations.
Board Setup Details
12
DP83TD510E-EVM User’s Guide
SNLU271A – MARCH 2020 – REVISED AUGUST 2020
Copyright © 2020 Texas Instruments Incorporated
