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5.2 DP83867 Schematic

CLK_OUT

18

GPIO_0

39

GPIO_1

40

GTX_CLK

29

INT/PWDN

44

JTAG_CLK

20

JTAG_TDI

23

JTAG_TDO

21

JTAG_TMS

22

LED_0

47

LED_1

46

LED_2

45

MDC

16

MDIO

17

PAD

49

RBIAS

12

RX_CLK

32

RX_CTRL

38

RX_D0/SGMII_COP

33

RX_D1/SGMII_CON

34

RX_D2/SGMII_SOP

35

RX_D3/SGMII_SON

36

TD_M_A

2

TD_M_B

5

TD_M_C

8

TD_M_D

11

TD_P_A

1

TD_P_B

4

TD_P_C

7

TD_P_D

10

TX_CTRL

37

TX_D0/SGMII_SIN

28

TX_D1/SGMII_SIP

27

TX_D2

26

TX_D3

25

VDD1P0

42

VDD1P0

31

VDD1P0

24

VDD1P0

6

VDDA1P8

48

VDDA1P8

13

VDDA2P5

3

VDDA2P5

9

VDDIO

30

VDDIO

41

VDDIO

19

X_I

15

X_O

14

RESET

43

DP83867ERGZR

U3

2.20k

R37

GND

GND

11.0k

R36

LED01
LED11
LED21

83867_RESET_N

10V
10uF

C45

50V
0.1uF

C47

25V
1uF

C46

+2V5_REG

GND

GND

MDIO

MDC

83867_RESET_N

867_TX_D0

10V
10uF

C63

50V
0.1uF

C65

25V
1uF

C64

10V
10uF

C55

50V
0.1uF

C57

25V
1uF

C56

GND

GND

GND

867_TX_D0

GND867

50V 0.1uF

C37

50V 0.1uF

C38

50V

0.1uF

C41

50V

0.1uF

C42

GND

GND

GND

GND

50V
0.1uF

C59

50V
0.1uF

C61

50V
0.1uF

C49

50V
0.1uF

C51

50V
0.1uF

C53

50V
0.1uF

C67

TD_A_P
TD_A_N

TD_B_P
TD_B_N

TD_C_P
TD_C_N

TD_D_P
TD_D_N

0

R38

LED21

470

R32

470

R34

LED11

LED01

2.49k

R33

GND867

GND

0.01

µ

F

1kV

C36

+1V0_867

+2V5_867

1.0M

R35

+1V0_REG

+1V0_867

+2V5_867

867_TX_CLK

867_TX_CTRL

867_TX_CLK

867_TX_CTRL

22

R80

22

R81

867_TX_D1
867_TX_D2
867_TX_D3

867_TX_D1
867_TX_D2
867_TX_D3

867_RX_CTRL
867_RX_CLK

867_RX_D0
867_RX_D1
867_RX_D2
867_RX_D3

22

R82

22

R83

22

R84

22

R85

812_TX_D0

812_TX_CLK

812_TX_CTRL

812_TX_D1
812_TX_D2
812_TX_D3

GND

5.76k

R94

VDDMAC

VDDIO_867

VDDIO_867

VDDIO_867

VDDIO_867

VDDIO_867

GND

RX_D0 = Mode 2

867_RX_D0

VDDIO_867

GND

5.76k

R15

RX_CTRL = Mode 3

867_RX_CTRL

VDDIO_867

2.49k

R18

2.49k

R20

0

L6

0

L7

0

L5

TD_A_N

TD_A_P

TD_B_P

TD_B_N

TD_C_N

TD_C_P

TD_D_P

TD_D_N

10nF

C48

10nF

C50

10nF

C52

10nF

C54

10nF

C58

10nF

C60

10nF

C62

10nF

C66

10nF

C68

27pF
50V

C43

27pF
50V

C44

10.0k

R14

MDCT3

MD3-

MD3+

MD2+

MD2-

MDCT2

MDCT4

MD4+

MD4-

MD1-

MD1+

MDCT1

YELLOW_CATHODE

YELLOW_ANODE

GREEN_CATHODE

GREEN_ANODE

MNT_1

MNT_2

J12

AR11-4647

1

2

Y2

Figure 5-2. DP83867 Schematic

Schematics

www.ti.com

10

DP83TC812EVM-MC User's Guide

SNLU292A – NOVEMBER 2020 – REVISED MARCH 2022

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Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for DP83TC812EVM-MC

Page 1: ...History 2 2 Introduction 3 2 1 Key Features 3 2 2 Operation Quick Setup 4 3 Board Setup Details 7 3 1 Block Diagram 7 3 2 Configuration Options 7 4 Definitions 8 5 Schematics 9 5 1 Main Block Schemat...

Page 2: ...10 Figure 5 3 Power Schematic 11 Figure 5 4 AFE Schematic 12 Figure 5 5 Comms Schematic 13 Figure 5 6 Hardware Schematic 14 Figure 6 1 Top Overlay 15 Figure 6 2 Bottom Overlay 16 1 Revision History NO...

Page 3: ...o 100BASE TX IEEE802 3bw Compliant IEEE802 3u Compliant RGMII Back to Back Configuration On board MSP430F5528 USB 2 MDIO Support Status LEDs DP83TC812 Link Link Activity DP83822 Link RJ 45 Power on In...

Page 4: ...D3P3 and VDD1P0 Place shunt on VDDMAC This supply can have adjustable voltages depending on location of shunt J1 for 3 3V operation J3 for 1 8V operation J5 for 2 5V operation Place shunts on J23 and...

Page 5: ...right most pin Cross connection rewrok required for Rev A board not required for Rev B current board Figure 2 5 On board MSP connections for MDIO and MDC 2 2 2 2 Downloading USB2MDIO for SMI The on bo...

Page 6: ...emonstrated in figure below Slave Mode Place shunt across pins 2 and 3 of J2 Figure 2 6 DP83TC812 configured as Master 2 2 4 Wake Selection DP83TC812 Place shunt in PU position at WAKE header shown to...

Page 7: ...RGMII Straps CLKOUT MSP430F5528 USB2MDIO USB MDIO MDC RGMII 1 0V LDO Figure 3 1 DP83TC812EVM MC Block Diagram 3 2 Configuration Options 3 2 1 Clock Configuration Onboard Clock The onboard crystal is...

Page 8: ...Data Clock RGMII Reduced Gigabyte Media Independent Interface SFD Start of Frame Detection VDDA Analog Core Supply Rail VDDIO Digital Supply Rail PD Pull down PU Pullup MC Micro controller Definition...

Page 9: ...14 RX_DV CRS_DV RX_CTRL 15 CLKOUT GPIO_2 16 GND_ESC 17 GND_ESC 18 NC 19 NC 20 NC 21 VDDMAC 22 RX_D3 23 RX_D2 24 RX_D1 25 RX_D0 26 RX_CLK 27 TX_CLK 28 TX_EN TX_CTRL 29 TX_D3 30 TX_D2 31 TX_D1 32 TX_D0...

Page 10: ...1uF C67 TD_A_P TD_A_N TD_B_P TD_B_N TD_C_P TD_C_N TD_D_P TD_D_N 0 R38 LED21 470 R32 470 R34 LED11 LED01 2 49k R33 GND867 GND 0 01 F 1kV C36 1V0_867 2V5_867 1 0M R35 1V0_REG 1V0_867 2V5_867 867_TX_CLK...

Page 11: ...LT1G 2 2k R66 1V0 TP8 1502 2 TP9 1502 2 2 2k R61 2 2k R62 IN 1 IN 2 PG 3 BIAS 4 EN 5 GND 6 SS 7 FB 8 OUT 9 OUT 10 PAD 11 TPS74701DRCR U7 25V 1uF C86 GND 3V3_REG 50V 0 1uF C82 50V 0 1uF C88 4 42k R68 1...

Page 12: ...1 00k R110 1 00k R109 1 0M R115 D1 EZAEG3W11AV D7 EZAEG3W11AV GND 1 2 S 1 S 2 S 3 S 4 S 5 S 6 J11 9 2304372 1 GND812 CON2_P CON2_N GND 1 00k R112 1 00k R111 100k R113 100k R114 1 2 3 4 200 H L1 100nF...

Page 13: ...R D22 HSMF C165 GND GND 470 R27 470 R99 P1 7 P1 6 P1 7 P1 6 SW1 SW1 SW2 SW3 SW4 SW2 SW3 SW4 INT INH 6 3 1 8 2 7 5 4 S1 219 4LPST P6 0 CB0 A0 1 P6 1 CB1 A1 2 P6 2 CB2 A2 3 P6 3 CB3 A3 4 P6 4 CB4 A4 5 P...

Page 14: ...e MCU wiring Pin 11 18 50 006 Change MCU MDIO wiring LOGO PCB Texas Instruments FID1 Fiducial FID5 Fiducial FID2 Fiducial FID3 Fiducial FID6 Fiducial FID4 Fiducial SH J1 M7582 05 SH J2 M7582 05 SH J3...

Page 15: ...6 Layout Figure 6 1 Top Overlay www ti com Schematics SNLU292A NOVEMBER 2020 REVISED MARCH 2022 Submit Document Feedback DP83TC812EVM MC User s Guide 15 Copyright 2022 Texas Instruments Incorporated...

Page 16: ...Figure 6 2 Bottom Overlay Schematics www ti com 16 DP83TC812EVM MC User s Guide SNLU292A NOVEMBER 2020 REVISED MARCH 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated...

Page 17: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 18: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 19: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 20: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 21: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 22: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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