Introduction
4
SNLU262 – December 2019
Copyright © 2019, Texas Instruments Incorporated
DP83826EVM User’s Guide
2
Introduction
The DP83826 is a low latency, deterministic, and low power Ethernet Physical Layer transceiver with
integrated PMD sublayers to support both 10BASE-Te and 100BASE-TX Ethernet protocols. The
DP83826 interfaces directly to twisted pair media via an external transformer and offers integrated cable
diagnostic tools, built-in self-test and loopback capabilities for ease of use. It interfaces to the MAC layer
through a Media Independent Interface (MII) or a Reduced MII (RMII) both in Master and Slave mode. The
50 MHz clock in RMII Master mode is synchronized to the MDI derived clock to improve the system's jitter.
The DP83826EVM will demonstrate all features of DP83826. The EVM supports 10BASE-Te and
100BASE-TX Ethernet protocols. The EVM includes connections to use the DP83826 MII and RMII pins
through header pins.
2.1
Key Features
•
100Base-TX, 10Base-Te with Auto-Negotiation and Force 100M Mode
•
Onboard Clock
•
Output Clock
•
Onboard MSP430F5529 for easy MDIO Register Access
•
Onboard MSP430F5528 for flashing firmware
•
LDO and External Power Supply Options
•
Status LEDs
•
100BASE-TX Data Transfer Over 150 Meters CAT5 Cable
•
Fiber Optic transceivers option for MDIO/MDC
•
EMI/EMC Compliance Testing Completed:
•
CISPR 22 Radiated Emissions Class B
•
CISPR 22 Conducted Emissions Class B
•
IEC 61000-4-2 ESD: ±8 kV contact, ±15 kV air
•
IEC 61000-4-4 EFT: ±4 kV @ 5 kHz, 100 kHz